Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10756 |
1 |
|
T16 |
125 |
|
T5 |
2 |
|
T19 |
1 |
| others[1] |
752 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
| others[2] |
839 |
1 |
|
T17 |
1 |
|
T39 |
14 |
|
T167 |
1 |
| others[3] |
1348 |
1 |
|
T5 |
2 |
|
T25 |
1 |
|
T39 |
13 |
| false |
424 |
1 |
|
T5 |
4 |
|
T38 |
1 |
|
T39 |
6 |
| true |
533 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2536 |
1 |
|
T16 |
24 |
|
T5 |
4 |
|
T39 |
10 |
| others[1] |
2502 |
1 |
|
T16 |
27 |
|
T5 |
2 |
|
T38 |
1 |
| others[2] |
2478 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
23 |
| others[3] |
4203 |
1 |
|
T1 |
1 |
|
T16 |
39 |
|
T5 |
2 |
| false |
1320 |
1 |
|
T16 |
12 |
|
T39 |
6 |
|
T167 |
1 |
| true |
1613 |
1 |
|
T15 |
1 |
|
T18 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10233 |
1 |
|
T2 |
1 |
|
T16 |
125 |
|
T17 |
1 |
| others[1] |
272 |
1 |
|
T87 |
1 |
|
T68 |
1 |
|
T130 |
1 |
| others[2] |
301 |
1 |
|
T25 |
1 |
|
T40 |
1 |
|
T61 |
1 |
| others[3] |
465 |
1 |
|
T1 |
1 |
|
T21 |
1 |
|
T42 |
1 |
| false |
140 |
1 |
|
T115 |
4 |
|
T216 |
1 |
|
T405 |
1 |
| true |
3241 |
1 |
|
T3 |
1 |
|
T15 |
1 |
|
T5 |
9 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10424 |
1 |
|
T16 |
125 |
|
T17 |
1 |
|
T31 |
1 |
| others[1] |
528 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T38 |
1 |
| others[2] |
480 |
1 |
|
T5 |
2 |
|
T40 |
1 |
|
T33 |
1 |
| others[3] |
773 |
1 |
|
T5 |
2 |
|
T19 |
1 |
|
T22 |
1 |
| false |
261 |
1 |
|
T39 |
3 |
|
T63 |
1 |
|
T113 |
4 |
| true |
2186 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10214 |
1 |
|
T16 |
125 |
|
T17 |
1 |
|
T22 |
1 |
| others[1] |
241 |
1 |
|
T19 |
1 |
|
T31 |
1 |
|
T87 |
1 |
| others[2] |
256 |
1 |
|
T18 |
1 |
|
T103 |
1 |
|
T32 |
1 |
| others[3] |
431 |
1 |
|
T68 |
2 |
|
T131 |
2 |
|
T115 |
20 |
| false |
143 |
1 |
|
T112 |
1 |
|
T115 |
9 |
|
T64 |
1 |
| true |
3367 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10215 |
1 |
|
T16 |
125 |
|
T19 |
1 |
|
T82 |
254 |
| others[1] |
249 |
1 |
|
T2 |
1 |
|
T25 |
1 |
|
T68 |
1 |
| others[2] |
244 |
1 |
|
T3 |
1 |
|
T33 |
1 |
|
T87 |
1 |
| others[3] |
428 |
1 |
|
T167 |
1 |
|
T103 |
2 |
|
T32 |
1 |
| false |
129 |
1 |
|
T115 |
3 |
|
T406 |
1 |
|
T407 |
1 |
| true |
3387 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10781 |
1 |
|
T16 |
125 |
|
T5 |
1 |
|
T19 |
1 |
| others[1] |
806 |
1 |
|
T3 |
1 |
|
T5 |
2 |
|
T39 |
12 |
| others[2] |
799 |
1 |
|
T39 |
8 |
|
T63 |
3 |
|
T112 |
1 |
| others[3] |
1355 |
1 |
|
T5 |
4 |
|
T25 |
1 |
|
T39 |
11 |
| false |
405 |
1 |
|
T17 |
1 |
|
T5 |
2 |
|
T38 |
1 |
| true |
506 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10719 |
1 |
|
T16 |
125 |
|
T5 |
2 |
|
T39 |
6 |
| others[1] |
778 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T38 |
1 |
| others[2] |
838 |
1 |
|
T17 |
1 |
|
T5 |
1 |
|
T19 |
1 |
| others[3] |
1304 |
1 |
|
T5 |
2 |
|
T39 |
13 |
|
T61 |
1 |
| false |
435 |
1 |
|
T5 |
3 |
|
T18 |
1 |
|
T39 |
5 |
| true |
525 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2516 |
1 |
|
T3 |
1 |
|
T16 |
31 |
|
T5 |
1 |
| others[1] |
2533 |
1 |
|
T16 |
18 |
|
T5 |
1 |
|
T25 |
1 |
| others[2] |
2471 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T16 |
25 |
| others[3] |
4213 |
1 |
|
T16 |
40 |
|
T5 |
4 |
|
T19 |
1 |
| false |
1306 |
1 |
|
T16 |
11 |
|
T5 |
1 |
|
T39 |
1 |
| true |
1560 |
1 |
|
T15 |
1 |
|
T18 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10217 |
1 |
|
T16 |
125 |
|
T82 |
254 |
|
T44 |
114 |
| others[1] |
245 |
1 |
|
T31 |
1 |
|
T34 |
1 |
|
T114 |
1 |
| others[2] |
281 |
1 |
|
T3 |
1 |
|
T22 |
1 |
|
T21 |
1 |
| others[3] |
448 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T19 |
1 |
| false |
147 |
1 |
|
T18 |
1 |
|
T115 |
3 |
|
T107 |
1 |
| true |
3261 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T5 |
9 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10394 |
1 |
|
T16 |
125 |
|
T39 |
3 |
|
T40 |
1 |
| others[1] |
438 |
1 |
|
T2 |
1 |
|
T5 |
4 |
|
T31 |
1 |
| others[2] |
465 |
1 |
|
T22 |
1 |
|
T24 |
1 |
|
T39 |
3 |
| others[3] |
796 |
1 |
|
T18 |
1 |
|
T23 |
1 |
|
T39 |
8 |
| false |
238 |
1 |
|
T39 |
5 |
|
T33 |
1 |
|
T114 |
1 |
| true |
2268 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10185 |
1 |
|
T16 |
125 |
|
T31 |
1 |
|
T33 |
1 |
| others[1] |
266 |
1 |
|
T68 |
1 |
|
T115 |
11 |
|
T408 |
1 |
| others[2] |
282 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T18 |
1 |
| others[3] |
430 |
1 |
|
T1 |
1 |
|
T38 |
1 |
|
T40 |
1 |
| false |
132 |
1 |
|
T3 |
1 |
|
T103 |
1 |
|
T28 |
1 |
| true |
3304 |
1 |
|
T17 |
1 |
|
T5 |
9 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10180 |
1 |
|
T16 |
125 |
|
T38 |
1 |
|
T82 |
254 |
| others[1] |
250 |
1 |
|
T1 |
1 |
|
T114 |
1 |
|
T115 |
14 |
| others[2] |
269 |
1 |
|
T167 |
1 |
|
T131 |
1 |
|
T62 |
1 |
| others[3] |
457 |
1 |
|
T2 |
1 |
|
T18 |
1 |
|
T25 |
1 |
| false |
138 |
1 |
|
T115 |
3 |
|
T128 |
1 |
|
T96 |
1 |
| true |
3305 |
1 |
|
T3 |
1 |
|
T15 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10720 |
1 |
|
T16 |
125 |
|
T25 |
1 |
|
T39 |
9 |
| others[1] |
821 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T19 |
1 |
| others[2] |
784 |
1 |
|
T5 |
4 |
|
T39 |
7 |
|
T40 |
1 |
| others[3] |
1350 |
1 |
|
T17 |
1 |
|
T5 |
4 |
|
T24 |
1 |
| false |
420 |
1 |
|
T2 |
1 |
|
T39 |
4 |
|
T63 |
2 |
| true |
504 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10737 |
1 |
|
T16 |
125 |
|
T5 |
3 |
|
T25 |
1 |
| others[1] |
822 |
1 |
|
T5 |
2 |
|
T38 |
1 |
|
T39 |
15 |
| others[2] |
795 |
1 |
|
T17 |
1 |
|
T39 |
8 |
|
T167 |
1 |
| others[3] |
1303 |
1 |
|
T2 |
1 |
|
T5 |
3 |
|
T39 |
12 |
| false |
399 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T19 |
1 |
| true |
543 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2570 |
1 |
|
T3 |
1 |
|
T16 |
32 |
|
T5 |
2 |
| others[1] |
2426 |
1 |
|
T16 |
21 |
|
T17 |
1 |
|
T5 |
3 |
| others[2] |
2473 |
1 |
|
T16 |
20 |
|
T5 |
1 |
|
T39 |
14 |
| others[3] |
4152 |
1 |
|
T16 |
41 |
|
T5 |
1 |
|
T19 |
1 |
| false |
1381 |
1 |
|
T2 |
1 |
|
T16 |
11 |
|
T5 |
2 |
| true |
1597 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10249 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T16 |
125 |
| others[1] |
289 |
1 |
|
T43 |
1 |
|
T32 |
1 |
|
T68 |
1 |
| others[2] |
269 |
1 |
|
T22 |
1 |
|
T31 |
1 |
|
T40 |
1 |
| others[3] |
431 |
1 |
|
T17 |
1 |
|
T19 |
1 |
|
T23 |
1 |
| false |
170 |
1 |
|
T2 |
1 |
|
T18 |
1 |
|
T21 |
1 |
| true |
3191 |
1 |
|
T3 |
1 |
|
T5 |
9 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10418 |
1 |
|
T1 |
1 |
|
T16 |
125 |
|
T5 |
1 |
| others[1] |
476 |
1 |
|
T5 |
1 |
|
T18 |
1 |
|
T39 |
3 |
| others[2] |
441 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T5 |
2 |
| others[3] |
768 |
1 |
|
T17 |
1 |
|
T5 |
1 |
|
T23 |
1 |
| false |
241 |
1 |
|
T114 |
1 |
|
T32 |
1 |
|
T113 |
6 |
| true |
2255 |
1 |
|
T3 |
1 |
|
T5 |
4 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10204 |
1 |
|
T16 |
125 |
|
T31 |
1 |
|
T82 |
254 |
| others[1] |
283 |
1 |
|
T17 |
1 |
|
T29 |
1 |
|
T115 |
9 |
| others[2] |
267 |
1 |
|
T25 |
1 |
|
T33 |
1 |
|
T30 |
1 |
| others[3] |
460 |
1 |
|
T15 |
1 |
|
T18 |
1 |
|
T40 |
1 |
| false |
133 |
1 |
|
T103 |
1 |
|
T68 |
1 |
|
T136 |
1 |
| true |
3252 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10192 |
1 |
|
T16 |
125 |
|
T25 |
1 |
|
T114 |
1 |
| others[1] |
239 |
1 |
|
T17 |
1 |
|
T40 |
1 |
|
T112 |
1 |
| others[2] |
259 |
1 |
|
T3 |
1 |
|
T115 |
13 |
|
T382 |
1 |
| others[3] |
448 |
1 |
|
T68 |
1 |
|
T115 |
25 |
|
T328 |
1 |
| false |
142 |
1 |
|
T68 |
1 |
|
T115 |
5 |
|
T188 |
1 |
| true |
3319 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10729 |
1 |
|
T16 |
125 |
|
T5 |
1 |
|
T39 |
9 |
| others[1] |
786 |
1 |
|
T5 |
3 |
|
T25 |
1 |
|
T39 |
8 |
| others[2] |
763 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T38 |
1 |
| others[3] |
1415 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T18 |
1 |
| false |
390 |
1 |
|
T17 |
1 |
|
T5 |
3 |
|
T39 |
1 |
| true |
516 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10763 |
1 |
|
T16 |
125 |
|
T5 |
3 |
|
T18 |
1 |
| others[1] |
778 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T39 |
6 |
| others[2] |
776 |
1 |
|
T25 |
1 |
|
T39 |
9 |
|
T11 |
1 |
| others[3] |
1330 |
1 |
|
T17 |
1 |
|
T5 |
3 |
|
T39 |
13 |
| false |
424 |
1 |
|
T5 |
2 |
|
T38 |
1 |
|
T39 |
6 |
| true |
528 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2484 |
1 |
|
T16 |
21 |
|
T5 |
2 |
|
T39 |
6 |
| others[1] |
2565 |
1 |
|
T16 |
35 |
|
T5 |
2 |
|
T39 |
8 |
| others[2] |
2528 |
1 |
|
T2 |
1 |
|
T16 |
21 |
|
T17 |
1 |
| others[3] |
4180 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T16 |
40 |
| false |
1284 |
1 |
|
T16 |
8 |
|
T39 |
4 |
|
T167 |
1 |
| true |
1558 |
1 |
|
T15 |
1 |
|
T18 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10210 |
1 |
|
T15 |
1 |
|
T16 |
125 |
|
T17 |
1 |
| others[1] |
275 |
1 |
|
T23 |
1 |
|
T32 |
1 |
|
T68 |
1 |
| others[2] |
286 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
| others[3] |
459 |
1 |
|
T18 |
1 |
|
T42 |
1 |
|
T114 |
1 |
| false |
136 |
1 |
|
T137 |
1 |
|
T115 |
6 |
|
T338 |
1 |
| true |
3233 |
1 |
|
T5 |
9 |
|
T19 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10408 |
1 |
|
T2 |
1 |
|
T16 |
125 |
|
T17 |
1 |
| others[1] |
441 |
1 |
|
T23 |
1 |
|
T24 |
1 |
|
T21 |
1 |
| others[2] |
461 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
2 |
| others[3] |
818 |
1 |
|
T5 |
1 |
|
T39 |
6 |
|
T43 |
1 |
| false |
244 |
1 |
|
T39 |
2 |
|
T63 |
1 |
|
T113 |
4 |
| true |
2227 |
1 |
|
T15 |
1 |
|
T5 |
4 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10215 |
1 |
|
T16 |
125 |
|
T38 |
1 |
|
T25 |
1 |
| others[1] |
265 |
1 |
|
T1 |
1 |
|
T33 |
1 |
|
T103 |
1 |
| others[2] |
237 |
1 |
|
T2 |
1 |
|
T18 |
1 |
|
T112 |
1 |
| others[3] |
414 |
1 |
|
T42 |
1 |
|
T87 |
1 |
|
T68 |
2 |
| false |
153 |
1 |
|
T115 |
7 |
|
T329 |
1 |
|
T117 |
1 |
| true |
3315 |
1 |
|
T3 |
1 |
|
T15 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10188 |
1 |
|
T3 |
1 |
|
T16 |
125 |
|
T40 |
1 |
| others[1] |
243 |
1 |
|
T68 |
1 |
|
T115 |
14 |
|
T328 |
1 |
| others[2] |
262 |
1 |
|
T32 |
1 |
|
T115 |
10 |
|
T375 |
1 |
| others[3] |
438 |
1 |
|
T68 |
1 |
|
T131 |
1 |
|
T137 |
1 |
| false |
128 |
1 |
|
T33 |
1 |
|
T62 |
1 |
|
T115 |
6 |
| true |
3340 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10759 |
1 |
|
T16 |
125 |
|
T17 |
1 |
|
T5 |
2 |
| others[1] |
804 |
1 |
|
T5 |
1 |
|
T39 |
8 |
|
T40 |
1 |
| others[2] |
795 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T25 |
1 |
| others[3] |
1289 |
1 |
|
T5 |
4 |
|
T19 |
1 |
|
T38 |
1 |
| false |
437 |
1 |
|
T5 |
1 |
|
T24 |
1 |
|
T39 |
8 |
| true |
515 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10723 |
1 |
|
T16 |
125 |
|
T5 |
4 |
|
T38 |
1 |
| others[1] |
752 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
| others[2] |
835 |
1 |
|
T25 |
1 |
|
T39 |
14 |
|
T167 |
1 |
| others[3] |
1345 |
1 |
|
T17 |
1 |
|
T5 |
4 |
|
T31 |
1 |
| false |
409 |
1 |
|
T39 |
5 |
|
T113 |
7 |
|
T50 |
1 |
| true |
535 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2549 |
1 |
|
T16 |
30 |
|
T17 |
1 |
|
T39 |
5 |
| others[1] |
2563 |
1 |
|
T16 |
25 |
|
T5 |
3 |
|
T39 |
10 |
| others[2] |
2427 |
1 |
|
T16 |
17 |
|
T5 |
2 |
|
T39 |
8 |
| others[3] |
4198 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
43 |
| false |
1305 |
1 |
|
T1 |
1 |
|
T16 |
10 |
|
T5 |
2 |
| true |
1557 |
1 |
|
T15 |
1 |
|
T18 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10214 |
1 |
|
T16 |
125 |
|
T40 |
1 |
|
T82 |
254 |
| others[1] |
265 |
1 |
|
T114 |
1 |
|
T103 |
1 |
|
T68 |
1 |
| others[2] |
262 |
1 |
|
T17 |
1 |
|
T31 |
1 |
|
T34 |
1 |
| others[3] |
445 |
1 |
|
T1 |
1 |
|
T115 |
13 |
|
T188 |
1 |
| false |
165 |
1 |
|
T22 |
1 |
|
T32 |
1 |
|
T68 |
1 |
| true |
3248 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T15 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |