Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10411 |
1 |
|
T16 |
125 |
|
T24 |
1 |
|
T39 |
3 |
| others[1] |
471 |
1 |
|
T5 |
1 |
|
T19 |
1 |
|
T23 |
1 |
| others[2] |
481 |
1 |
|
T2 |
1 |
|
T39 |
5 |
|
T167 |
1 |
| others[3] |
773 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T17 |
1 |
| false |
268 |
1 |
|
T103 |
1 |
|
T63 |
1 |
|
T113 |
4 |
| true |
2195 |
1 |
|
T15 |
1 |
|
T5 |
7 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10188 |
1 |
|
T16 |
125 |
|
T31 |
1 |
|
T82 |
254 |
| others[1] |
269 |
1 |
|
T1 |
1 |
|
T17 |
1 |
|
T38 |
1 |
| others[2] |
264 |
1 |
|
T19 |
1 |
|
T25 |
1 |
|
T32 |
1 |
| others[3] |
448 |
1 |
|
T18 |
1 |
|
T22 |
1 |
|
T42 |
1 |
| false |
148 |
1 |
|
T115 |
5 |
|
T107 |
1 |
|
T109 |
1 |
| true |
3282 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10189 |
1 |
|
T16 |
125 |
|
T82 |
254 |
|
T44 |
114 |
| others[1] |
233 |
1 |
|
T50 |
1 |
|
T115 |
8 |
|
T374 |
1 |
| others[2] |
278 |
1 |
|
T1 |
1 |
|
T115 |
10 |
|
T376 |
1 |
| others[3] |
440 |
1 |
|
T3 |
1 |
|
T21 |
1 |
|
T40 |
1 |
| false |
131 |
1 |
|
T19 |
1 |
|
T87 |
1 |
|
T68 |
1 |
| true |
3328 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10748 |
1 |
|
T16 |
125 |
|
T38 |
1 |
|
T39 |
8 |
| others[1] |
796 |
1 |
|
T5 |
4 |
|
T39 |
12 |
|
T63 |
4 |
| others[2] |
775 |
1 |
|
T3 |
1 |
|
T5 |
2 |
|
T25 |
1 |
| others[3] |
1353 |
1 |
|
T5 |
3 |
|
T19 |
1 |
|
T39 |
12 |
| false |
401 |
1 |
|
T17 |
1 |
|
T39 |
2 |
|
T63 |
1 |
| true |
526 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10729 |
1 |
|
T16 |
125 |
|
T5 |
2 |
|
T39 |
9 |
| others[1] |
815 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T5 |
1 |
| others[2] |
815 |
1 |
|
T5 |
3 |
|
T38 |
1 |
|
T39 |
7 |
| others[3] |
1304 |
1 |
|
T2 |
1 |
|
T5 |
2 |
|
T39 |
11 |
| false |
403 |
1 |
|
T5 |
1 |
|
T39 |
4 |
|
T11 |
1 |
| true |
533 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2485 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T16 |
28 |
| others[1] |
2524 |
1 |
|
T16 |
30 |
|
T5 |
4 |
|
T25 |
1 |
| others[2] |
2550 |
1 |
|
T2 |
1 |
|
T16 |
17 |
|
T5 |
3 |
| others[3] |
4217 |
1 |
|
T16 |
38 |
|
T17 |
1 |
|
T5 |
2 |
| false |
1265 |
1 |
|
T16 |
12 |
|
T39 |
3 |
|
T167 |
1 |
| true |
1558 |
1 |
|
T15 |
1 |
|
T18 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10220 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T16 |
125 |
| others[1] |
274 |
1 |
|
T19 |
1 |
|
T131 |
1 |
|
T115 |
12 |
| others[2] |
276 |
1 |
|
T31 |
1 |
|
T61 |
1 |
|
T136 |
1 |
| others[3] |
477 |
1 |
|
T43 |
1 |
|
T34 |
1 |
|
T50 |
1 |
| false |
136 |
1 |
|
T22 |
1 |
|
T62 |
1 |
|
T115 |
2 |
| true |
3216 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10429 |
1 |
|
T2 |
1 |
|
T16 |
125 |
|
T31 |
1 |
| others[1] |
468 |
1 |
|
T5 |
1 |
|
T18 |
1 |
|
T39 |
3 |
| others[2] |
460 |
1 |
|
T24 |
1 |
|
T39 |
2 |
|
T103 |
1 |
| others[3] |
807 |
1 |
|
T5 |
2 |
|
T19 |
1 |
|
T39 |
5 |
| false |
240 |
1 |
|
T5 |
3 |
|
T21 |
1 |
|
T39 |
3 |
| true |
2195 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10197 |
1 |
|
T16 |
125 |
|
T31 |
1 |
|
T21 |
1 |
| others[1] |
271 |
1 |
|
T19 |
1 |
|
T103 |
2 |
|
T68 |
2 |
| others[2] |
249 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T15 |
1 |
| others[3] |
457 |
1 |
|
T42 |
1 |
|
T32 |
1 |
|
T30 |
1 |
| false |
128 |
1 |
|
T18 |
1 |
|
T40 |
1 |
|
T131 |
1 |
| true |
3297 |
1 |
|
T3 |
1 |
|
T5 |
9 |
|
T38 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10182 |
1 |
|
T2 |
1 |
|
T16 |
125 |
|
T33 |
1 |
| others[1] |
271 |
1 |
|
T3 |
1 |
|
T18 |
1 |
|
T103 |
1 |
| others[2] |
264 |
1 |
|
T17 |
1 |
|
T32 |
1 |
|
T68 |
1 |
| others[3] |
405 |
1 |
|
T25 |
1 |
|
T68 |
1 |
|
T115 |
13 |
| false |
147 |
1 |
|
T1 |
1 |
|
T21 |
1 |
|
T40 |
1 |
| true |
3330 |
1 |
|
T15 |
1 |
|
T5 |
9 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10775 |
1 |
|
T16 |
125 |
|
T5 |
2 |
|
T38 |
1 |
| others[1] |
805 |
1 |
|
T5 |
2 |
|
T19 |
1 |
|
T25 |
1 |
| others[2] |
784 |
1 |
|
T39 |
10 |
|
T63 |
1 |
|
T113 |
18 |
| others[3] |
1339 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
| false |
401 |
1 |
|
T39 |
5 |
|
T63 |
2 |
|
T113 |
8 |
| true |
495 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10775 |
1 |
|
T16 |
125 |
|
T17 |
1 |
|
T5 |
3 |
| others[1] |
806 |
1 |
|
T5 |
2 |
|
T19 |
1 |
|
T39 |
5 |
| others[2] |
792 |
1 |
|
T5 |
1 |
|
T18 |
1 |
|
T39 |
10 |
| others[3] |
1318 |
1 |
|
T3 |
1 |
|
T5 |
2 |
|
T31 |
1 |
| false |
380 |
1 |
|
T5 |
1 |
|
T39 |
4 |
|
T11 |
1 |
| true |
528 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2456 |
1 |
|
T2 |
1 |
|
T16 |
21 |
|
T5 |
1 |
| others[1] |
2542 |
1 |
|
T16 |
31 |
|
T17 |
1 |
|
T5 |
1 |
| others[2] |
2600 |
1 |
|
T1 |
1 |
|
T16 |
21 |
|
T5 |
4 |
| others[3] |
4200 |
1 |
|
T16 |
41 |
|
T5 |
2 |
|
T25 |
1 |
| false |
1299 |
1 |
|
T3 |
1 |
|
T16 |
11 |
|
T5 |
1 |
| true |
1502 |
1 |
|
T15 |
1 |
|
T18 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10216 |
1 |
|
T15 |
1 |
|
T16 |
125 |
|
T33 |
1 |
| others[1] |
283 |
1 |
|
T167 |
1 |
|
T112 |
1 |
|
T28 |
1 |
| others[2] |
269 |
1 |
|
T17 |
1 |
|
T38 |
1 |
|
T40 |
1 |
| others[3] |
475 |
1 |
|
T3 |
1 |
|
T31 |
1 |
|
T25 |
1 |
| false |
157 |
1 |
|
T115 |
4 |
|
T316 |
1 |
|
T117 |
1 |
| true |
3199 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
9 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10425 |
1 |
|
T16 |
125 |
|
T39 |
4 |
|
T40 |
1 |
| others[1] |
437 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
2 |
| others[2] |
474 |
1 |
|
T24 |
1 |
|
T39 |
6 |
|
T43 |
1 |
| others[3] |
741 |
1 |
|
T5 |
1 |
|
T39 |
3 |
|
T51 |
1 |
| false |
260 |
1 |
|
T3 |
1 |
|
T5 |
2 |
|
T38 |
1 |
| true |
2262 |
1 |
|
T15 |
1 |
|
T17 |
1 |
|
T5 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10178 |
1 |
|
T16 |
125 |
|
T38 |
1 |
|
T21 |
1 |
| others[1] |
248 |
1 |
|
T2 |
1 |
|
T31 |
1 |
|
T103 |
1 |
| others[2] |
279 |
1 |
|
T15 |
1 |
|
T103 |
1 |
|
T115 |
12 |
| others[3] |
440 |
1 |
|
T22 |
1 |
|
T51 |
1 |
|
T114 |
1 |
| false |
142 |
1 |
|
T19 |
1 |
|
T32 |
1 |
|
T115 |
7 |
| true |
3312 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10191 |
1 |
|
T2 |
1 |
|
T16 |
125 |
|
T21 |
1 |
| others[1] |
221 |
1 |
|
T131 |
1 |
|
T115 |
5 |
|
T376 |
1 |
| others[2] |
259 |
1 |
|
T3 |
1 |
|
T25 |
1 |
|
T68 |
1 |
| others[3] |
415 |
1 |
|
T1 |
1 |
|
T18 |
1 |
|
T38 |
1 |
| false |
112 |
1 |
|
T103 |
1 |
|
T68 |
1 |
|
T115 |
5 |
| true |
3401 |
1 |
|
T15 |
1 |
|
T17 |
1 |
|
T5 |
9 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10753 |
1 |
|
T16 |
125 |
|
T5 |
2 |
|
T39 |
6 |
| others[1] |
800 |
1 |
|
T5 |
1 |
|
T39 |
10 |
|
T11 |
1 |
| others[2] |
771 |
1 |
|
T25 |
1 |
|
T39 |
12 |
|
T63 |
3 |
| others[3] |
1325 |
1 |
|
T17 |
1 |
|
T5 |
6 |
|
T19 |
1 |
| false |
434 |
1 |
|
T3 |
1 |
|
T38 |
1 |
|
T39 |
4 |
| true |
516 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10721 |
1 |
|
T15 |
1 |
|
T16 |
125 |
|
T17 |
1 |
| others[1] |
797 |
1 |
|
T39 |
7 |
|
T114 |
1 |
|
T63 |
5 |
| others[2] |
777 |
1 |
|
T5 |
4 |
|
T38 |
1 |
|
T25 |
1 |
| others[3] |
1352 |
1 |
|
T3 |
1 |
|
T5 |
4 |
|
T24 |
1 |
| false |
413 |
1 |
|
T39 |
2 |
|
T87 |
1 |
|
T63 |
1 |
| true |
539 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2476 |
1 |
|
T1 |
1 |
|
T16 |
18 |
|
T5 |
1 |
| others[1] |
2609 |
1 |
|
T16 |
27 |
|
T5 |
2 |
|
T39 |
9 |
| others[2] |
2507 |
1 |
|
T3 |
1 |
|
T16 |
27 |
|
T17 |
1 |
| others[3] |
4069 |
1 |
|
T2 |
1 |
|
T16 |
43 |
|
T5 |
4 |
| false |
1326 |
1 |
|
T16 |
10 |
|
T5 |
1 |
|
T39 |
4 |
| true |
1612 |
1 |
|
T15 |
1 |
|
T18 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10184 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T16 |
125 |
| others[1] |
281 |
1 |
|
T22 |
1 |
|
T103 |
2 |
|
T32 |
1 |
| others[2] |
287 |
1 |
|
T38 |
1 |
|
T24 |
1 |
|
T21 |
1 |
| others[3] |
458 |
1 |
|
T17 |
1 |
|
T42 |
1 |
|
T33 |
1 |
| false |
137 |
1 |
|
T115 |
9 |
|
T375 |
1 |
|
T337 |
1 |
| true |
3252 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T5 |
9 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10397 |
1 |
|
T16 |
125 |
|
T5 |
1 |
|
T39 |
1 |
| others[1] |
485 |
1 |
|
T17 |
1 |
|
T5 |
1 |
|
T25 |
1 |
| others[2] |
501 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T5 |
1 |
| others[3] |
793 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
1 |
| false |
252 |
1 |
|
T5 |
1 |
|
T23 |
1 |
|
T39 |
2 |
| true |
2171 |
1 |
|
T5 |
4 |
|
T18 |
1 |
|
T38 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10203 |
1 |
|
T2 |
1 |
|
T16 |
125 |
|
T42 |
1 |
| others[1] |
243 |
1 |
|
T15 |
1 |
|
T114 |
1 |
|
T103 |
1 |
| others[2] |
289 |
1 |
|
T31 |
1 |
|
T68 |
2 |
|
T115 |
15 |
| others[3] |
447 |
1 |
|
T18 |
1 |
|
T33 |
1 |
|
T51 |
1 |
| false |
134 |
1 |
|
T3 |
1 |
|
T115 |
4 |
|
T67 |
7 |
| true |
3283 |
1 |
|
T1 |
1 |
|
T17 |
1 |
|
T5 |
9 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10184 |
1 |
|
T3 |
1 |
|
T16 |
125 |
|
T17 |
1 |
| others[1] |
274 |
1 |
|
T115 |
12 |
|
T214 |
1 |
|
T64 |
1 |
| others[2] |
240 |
1 |
|
T32 |
1 |
|
T68 |
3 |
|
T115 |
9 |
| others[3] |
402 |
1 |
|
T68 |
2 |
|
T131 |
2 |
|
T137 |
1 |
| false |
138 |
1 |
|
T115 |
4 |
|
T64 |
1 |
|
T105 |
1 |
| true |
3361 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10758 |
1 |
|
T16 |
125 |
|
T5 |
2 |
|
T21 |
1 |
| others[1] |
829 |
1 |
|
T17 |
1 |
|
T5 |
1 |
|
T39 |
7 |
| others[2] |
784 |
1 |
|
T5 |
2 |
|
T19 |
1 |
|
T38 |
1 |
| others[3] |
1326 |
1 |
|
T3 |
1 |
|
T5 |
2 |
|
T39 |
13 |
| false |
399 |
1 |
|
T5 |
2 |
|
T39 |
8 |
|
T113 |
14 |
| true |
503 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T15 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |