Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	232320	1		T1	269		T3	479		T4	340
auto[FlashEraseBank]	251630	1		T1	179		T2	1		T3	361

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	266110	1		T1	240		T2	1		T3	840
auto[FlashOpProgram]	197370	1		T1	208		T4	320		T15	39
auto[FlashOpErase]	16470	1		T4	12		T16	189		T5	4
auto[FlashOpInvalid]	4000	1		T85	200		T86	200		T276	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	266110	1		T1	240		T2	1		T3	840
op[FlashOpProgram]	197370	1		T1	208		T4	320		T15	39
op[FlashOpErase]	16470	1		T4	12		T16	189		T5	4
read_erase_read	716	1		T20	1		T22	11		T27	1
read_prog_read	1266	1		T15	39		T23	1		T24	2

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	340699	1		T1	322		T2	1		T3	840
auto[FlashPartInfo]	139563	1		T1	120		T4	340		T15	84
auto[FlashPartInfo1]	874	1		T1	1		T21	1		T40	2
auto[FlashPartInfo2]	2814	1		T1	5		T18	3		T22	1

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	201055	1		T1	188		T2	1		T3	840
auto[FlashPartData]	auto[FlashOpProgram]	132027	1		T1	134		T5	4		T18	1
auto[FlashPartData]	auto[FlashOpErase]	3711	1		T5	4		T22	34		T63	3
auto[FlashPartData]	auto[FlashOpInvalid]	3906	1		T85	194		T86	196		T276	194
auto[FlashPartInfo]	auto[FlashOpRead]	62877	1		T1	48		T4	8		T15	45
auto[FlashPartInfo]	auto[FlashOpProgram]	63882	1		T1	72		T4	320		T15	39
auto[FlashPartInfo]	auto[FlashOpErase]	12716	1		T4	12		T16	189		T20	13
auto[FlashPartInfo]	auto[FlashOpInvalid]	88	1		T85	6		T86	4		T276	6
auto[FlashPartInfo1]	auto[FlashOpRead]	706	1		T1	1		T21	1		T40	2
auto[FlashPartInfo1]	auto[FlashOpProgram]	164	1		T48	32		T118	32		T119	32
auto[FlashPartInfo1]	auto[FlashOpErase]	2	1		T95	1		T411	1		-	-
auto[FlashPartInfo1]	auto[FlashOpInvalid]	2	1		T95	2		-	-		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1472	1		T1	3		T22	1		T23	1
auto[FlashPartInfo2]	auto[FlashOpProgram]	1297	1		T1	2		T18	3		T87	6
auto[FlashPartInfo2]	auto[FlashOpErase]	41	1		T64	1		T128	1		T89	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	4	1		T412	2		T413	2		-	-