Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.48	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	4	28	87.50

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	4	28	87.50	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31779	1		T16	368		T5	1		T24	2
auto[1]	20	1		T117	1		T102	2		T333	1
auto[2]	151	1		T43	2		T281	26		T334	1
auto[3]	243	1		T22	42		T42	3		T34	1

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	8079	1		T16	92		T22	13		T82	204
evic_idx[1]	8043	1		T16	92		T22	11		T42	1
evic_idx[2]	8034	1		T16	92		T22	7		T42	1
evic_idx[3]	8037	1		T16	92		T5	1		T22	11

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	31172	1		T16	368		T22	42		T82	816
evic_op[2]	473	1		T5	1		T24	2		T42	3

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	4	28	87.50	4

Automatically Generated Cross Bins for evic_all_cross

Element holes

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
*	[evic_op[1]]	[auto[1]]	--	--	4

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7730	1		T16	92		T82	204		T44	92
evic_idx[0]	evic_op[1]	auto[2]	32	1		T335	29		T336	3		-	-
evic_idx[0]	evic_op[1]	auto[3]	68	1		T22	13		T278	29		T337	3
evic_idx[0]	evic_op[2]	auto[0]	78	1		T121	4		T338	9		T49	4
evic_idx[0]	evic_op[2]	auto[1]	6	1		T102	1		T333	1		T339	1
evic_idx[0]	evic_op[2]	auto[2]	16	1		T281	6		T334	1		T340	5
evic_idx[0]	evic_op[2]	auto[3]	12	1		T341	1		T342	1		T343	1
evic_idx[1]	evic_op[1]	auto[0]	7731	1		T16	92		T82	204		T44	92
evic_idx[1]	evic_op[1]	auto[2]	12	1		T335	9		T336	3		-	-
evic_idx[1]	evic_op[1]	auto[3]	48	1		T22	11		T278	15		T337	3
evic_idx[1]	evic_op[2]	auto[0]	76	1		T121	4		T338	9		T49	4
evic_idx[1]	evic_op[2]	auto[1]	6	1		T334	1		T339	1		T344	1
evic_idx[1]	evic_op[2]	auto[2]	22	1		T43	1		T281	8		T340	9
evic_idx[1]	evic_op[2]	auto[3]	11	1		T42	1		T34	1		T35	1
evic_idx[2]	evic_op[1]	auto[0]	7732	1		T16	92		T82	204		T44	92
evic_idx[2]	evic_op[1]	auto[2]	6	1		T335	5		T336	1		-	-
evic_idx[2]	evic_op[1]	auto[3]	43	1		T22	7		T278	12		T337	4
evic_idx[2]	evic_op[2]	auto[0]	79	1		T63	1		T136	1		T121	4
evic_idx[2]	evic_op[2]	auto[1]	2	1		T334	1		T344	1		-	-
evic_idx[2]	evic_op[2]	auto[2]	23	1		T43	1		T281	4		T340	7
evic_idx[2]	evic_op[2]	auto[3]	12	1		T42	1		T35	1		T116	1
evic_idx[3]	evic_op[1]	auto[0]	7730	1		T16	92		T82	204		T44	92
evic_idx[3]	evic_op[1]	auto[2]	3	1		T335	2		T336	1		-	-
evic_idx[3]	evic_op[1]	auto[3]	37	1		T22	11		T278	10		T337	2
evic_idx[3]	evic_op[2]	auto[0]	91	1		T5	1		T24	2		T121	4
evic_idx[3]	evic_op[2]	auto[1]	6	1		T117	1		T102	1		T339	1
evic_idx[3]	evic_op[2]	auto[2]	21	1		T281	8		T340	5		T345	4
evic_idx[3]	evic_op[2]	auto[3]	12	1		T42	1		T346	1		T347	1