Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv



Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 5 0 5 100.00
Crosses 6 0 6 100.00


Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
instr_type_cp 3 0 3 100.00 100 1 1 0
key_cp 2 0 2 100.00 100 1 1 2


Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
key_instr_cross 6 0 6 100.00 100 1 1 0


Summary for Variable instr_type_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for instr_type_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
others 5136 1 T39 149 T56 1 T59 38
instr_types[0] 6083 1 T39 170 T59 212 T60 199
instr_types[1] 4609213 1 T1 124 T3 16117 T15 4



Summary for Variable key_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for key_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4618403 1 T1 124 T3 16117 T15 4
auto[1] 2029 1 T39 200 T59 183 T60 169



Summary for Cross key_instr_cross

Samples crossed: key_cp instr_type_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 6 0 6 100.00


Automatically Generated Cross Bins for key_instr_cross

Bins
key_cpinstr_type_cpCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] others 4827 1 T39 127 T56 1 T59 13
auto[0] instr_types[0] 5211 1 T39 106 T59 132 T60 93
auto[0] instr_types[1] 4608365 1 T1 124 T3 16117 T15 4
auto[1] others 309 1 T39 22 T59 25 T60 23
auto[1] instr_types[0] 872 1 T39 64 T59 80 T60 106
auto[1] instr_types[1] 848 1 T39 114 T59 78 T60 40

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%