Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	17606	1		T323	2741		T201	2880		T324	6713
rd_lvl[2]	35335	1		T323	1794		T201	1784		T325	5730
rd_lvl[3]	28696	1		T130	1242		T216	944		T277	1314
rd_lvl[4]	32506	1		T3	2453		T130	3174		T216	1844
rd_lvl[5]	18663	1		T3	907		T130	355		T216	126
rd_lvl[6]	13191	1		T130	80		T216	482		T326	918
rd_lvl[7]	11011	1		T216	755		T127	594		T305	59
rd_lvl[8]	22112	1		T32	1572		T216	186		T327	1663
rd_lvl[9]	12048	1		T32	342		T28	650		T328	602
rd_lvl[10]	5801	1		T28	340		T280	321		T328	410
rd_lvl[11]	5578	1		T31	266		T280	603		T329	616
rd_lvl[12]	4907	1		T31	880		T28	9		T280	1
rd_lvl[13]	4593	1		T130	80		T29	496		T280	97
rd_lvl[14]	5876	1		T29	530		T30	641		T329	62
rd_lvl[15]	4787	1		T30	453		T330	866		T331	16