Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	313821	1		T1	2		T2	2		T3	3361
all_pins[1]	313821	1		T1	2		T2	2		T3	3361
all_pins[2]	313821	1		T1	2		T2	2		T3	3361
all_pins[3]	313821	1		T1	2		T2	2		T3	3361
all_pins[4]	313821	1		T1	2		T2	2		T3	3361
all_pins[5]	313821	1		T1	2		T2	2		T3	3361

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1554416	1		T1	12		T2	12		T3	15966
values[0x1]	328510	1		T3	4200		T19	1174		T31	2292
transitions[0x0=>0x1]	295370	1		T3	3360		T19	1174		T31	2292
transitions[0x1=>0x0]	295359	1		T3	3360		T19	1174		T31	2292

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	313688	1		T1	2		T2	2		T3	3361
all_pins[0]	values[0x1]	133	1		T268	3		T269	2		T317	4
all_pins[0]	transitions[0x0=>0x1]	61	1		T268	1		T317	3		T318	2
all_pins[0]	transitions[0x1=>0x0]	101	1		T268	1		T269	3		T317	2
all_pins[1]	values[0x0]	313648	1		T1	2		T2	2		T3	3361
all_pins[1]	values[0x1]	173	1		T268	3		T269	5		T317	3
all_pins[1]	transitions[0x0=>0x1]	151	1		T268	3		T269	5		T317	3
all_pins[1]	transitions[0x1=>0x0]	1483	1		T30	43		T330	39		T350	506
all_pins[2]	values[0x0]	312316	1		T1	2		T2	2		T3	3361
all_pins[2]	values[0x1]	1505	1		T30	43		T330	39		T350	506
all_pins[2]	transitions[0x0=>0x1]	35	1		T319	1		T321	1		T351	2
all_pins[2]	transitions[0x1=>0x0]	223237	1		T3	3360		T31	1146		T32	1914
all_pins[3]	values[0x0]	89114	1		T1	2		T2	2		T3	1
all_pins[3]	values[0x1]	224707	1		T3	3360		T31	1146		T32	1914
all_pins[3]	transitions[0x0=>0x1]	193189	1		T3	2520		T31	1146		T32	957
all_pins[3]	transitions[0x1=>0x0]	70414	1		T19	1174		T31	1146		T25	1020
all_pins[4]	values[0x0]	211889	1		T1	2		T2	2		T3	2521
all_pins[4]	values[0x1]	101932	1		T3	840		T19	1174		T31	1146
all_pins[4]	transitions[0x0=>0x1]	101907	1		T3	840		T19	1174		T31	1146
all_pins[4]	transitions[0x1=>0x0]	35	1		T269	1		T317	1		T318	3
all_pins[5]	values[0x0]	313761	1		T1	2		T2	2		T3	3361
all_pins[5]	values[0x1]	60	1		T269	1		T317	1		T318	3
all_pins[5]	transitions[0x0=>0x1]	27	1		T317	1		T318	1		T321	2
all_pins[5]	transitions[0x1=>0x0]	89	1		T268	2		T269	1		T317	3