Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	281	1		T268	4		T269	4		T317	7
all_values[1]	281	1		T268	4		T269	4		T317	7
all_values[2]	281	1		T268	4		T269	4		T317	7
all_values[3]	281	1		T268	4		T269	4		T317	7
all_values[4]	281	1		T268	4		T269	4		T317	7
all_values[5]	281	1		T268	4		T269	4		T317	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	901	1		T268	13		T269	10		T317	20
auto[1]	785	1		T268	11		T269	14		T317	22

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	557	1		T268	11		T269	5		T317	17
auto[1]	1129	1		T268	13		T269	19		T317	25

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1006	1		T268	16		T269	13		T317	29
auto[1]	680	1		T268	8		T269	11		T317	13

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	94	1		T268	2		T269	1		T317	1
all_values[0]	auto[0]	auto[1]	auto[1]	69	1		T268	1		T269	1		T317	3
all_values[0]	auto[1]	auto[0]	auto[1]	73	1		T268	1		T317	1		T318	1
all_values[0]	auto[1]	auto[1]	auto[1]	45	1		T269	2		T317	2		T318	2
all_values[1]	auto[0]	auto[0]	auto[1]	82	1		T268	1		T317	3		T318	3
all_values[1]	auto[0]	auto[1]	auto[1]	90	1		T268	1		T269	2		T317	2
all_values[1]	auto[1]	auto[0]	auto[1]	55	1		T317	2		T318	1		T319	1
all_values[1]	auto[1]	auto[1]	auto[1]	54	1		T268	2		T269	2		T318	2
all_values[2]	auto[0]	auto[0]	auto[0]	103	1		T268	4		T269	3		T317	2
all_values[2]	auto[0]	auto[1]	auto[0]	77	1		T317	3		T318	1		T319	1
all_values[2]	auto[1]	auto[0]	auto[1]	58	1		T269	1		T317	1		T318	1
all_values[2]	auto[1]	auto[1]	auto[1]	43	1		T317	1		T319	1		T320	1
all_values[3]	auto[0]	auto[0]	auto[0]	87	1		T268	2		T269	1		T317	3
all_values[3]	auto[0]	auto[1]	auto[0]	72	1		T268	1		T269	1		T317	3
all_values[3]	auto[1]	auto[0]	auto[1]	63	1		T269	2		T317	1		T318	2
all_values[3]	auto[1]	auto[1]	auto[1]	59	1		T268	1		T318	1		T319	2
all_values[4]	auto[0]	auto[0]	auto[0]	50	1		T268	2		T317	2		T318	2
all_values[4]	auto[0]	auto[0]	auto[1]	24	1		T269	1		T317	1		T318	2
all_values[4]	auto[0]	auto[1]	auto[0]	51	1		T317	1		T318	1		T319	2
all_values[4]	auto[0]	auto[1]	auto[1]	31	1		T269	1		T320	1		T321	1
all_values[4]	auto[1]	auto[0]	auto[1]	71	1		T317	1		T318	1		T319	3
all_values[4]	auto[1]	auto[1]	auto[1]	54	1		T268	2		T269	2		T317	2
all_values[5]	auto[0]	auto[0]	auto[0]	54	1		T317	1		T318	1		T319	2
all_values[5]	auto[0]	auto[0]	auto[1]	24	1		T269	1		T318	1		T322	1
all_values[5]	auto[0]	auto[1]	auto[0]	63	1		T268	2		T317	2		T318	2
all_values[5]	auto[0]	auto[1]	auto[1]	35	1		T269	1		T317	2		T318	1
all_values[5]	auto[1]	auto[0]	auto[1]	63	1		T268	1		T317	1		T319	1
all_values[5]	auto[1]	auto[1]	auto[1]	42	1		T268	1		T269	2		T317	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal