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 LINE       139
 EXPRESSION (read_buf[0].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       139
 EXPRESSION (read_buf[1].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       139
 EXPRESSION (read_buf[2].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       139
 EXPRESSION (read_buf[3].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       140
 EXPRESSION (read_buf[0].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       140
 EXPRESSION (read_buf[1].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       140
 EXPRESSION (read_buf[2].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       140
 EXPRESSION (read_buf[3].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       145
 EXPRESSION ((read_buf[0].attr == Invalid) | ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT33,T62,T214
10CoveredT1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[0].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110CoveredT204
111CoveredT33,T62,T214

 LINE       145
 SUB-EXPRESSION (read_buf[0].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       145
 EXPRESSION ((read_buf[1].attr == Invalid) | ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT42,T33,T62
10CoveredT1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[1].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT42,T33,T62

 LINE       145
 SUB-EXPRESSION (read_buf[1].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       145
 EXPRESSION ((read_buf[2].attr == Invalid) | ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT33,T62,T214
10CoveredT1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[2].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT33,T62,T214

 LINE       145
 SUB-EXPRESSION (read_buf[2].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       145
 EXPRESSION ((read_buf[3].attr == Invalid) | ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT33,T61,T62
10CoveredT1,T2,T3

 LINE       145
 SUB-EXPRESSION (read_buf[3].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       145
 SUB-EXPRESSION ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT33,T61,T62

 LINE       145
 SUB-EXPRESSION (read_buf[3].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       153
 EXPRESSION (buf_invalid[1] & ((~|buf_invalid[0])))
             -------1------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       153
 EXPRESSION (buf_invalid[2] & ((~|buf_invalid[(2 - 1):0])))
             -------1------   --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       153
 EXPRESSION (buf_invalid[3] & ((~|buf_invalid[(3 - 1):0])))
             -------1------   --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       166
 EXPRESSION ((((|buf_invalid_alloc)) | all_buf_dependency) ? '0 : ((buf_valid & (~buf_dependency))))
             ----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       166
 SUB-EXPRESSION (((|buf_invalid_alloc)) | all_buf_dependency)
                 -----------1----------   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       166
 EXPRESSION (req_o & no_match)
             --1--   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       185
 EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       192
 EXPRESSION (read_buf[0].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       192
 EXPRESSION (read_buf[1].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       192
 EXPRESSION (read_buf[2].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       192
 EXPRESSION (read_buf[3].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       193
 EXPRESSION (read_buf[0].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       193
 EXPRESSION (read_buf[1].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       193
 EXPRESSION (read_buf[2].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       193
 EXPRESSION (read_buf[3].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[0] | buf_wip[0]) & 
      4  (read_buf[0].addr == flash_word_addr) & 
      5  ((~read_buf[0].err)) & 
      6  gen_buf_match[0].part_match & 
      7  gen_buf_match[0].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT1,T2,T3
1011111Not Covered
1101111CoveredT16,T22,T82
1110111CoveredT1,T2,T3
1111011CoveredT33,T212,T213
1111101Not Covered
1111110CoveredT33,T167,T112
1111111CoveredT1,T2,T3

 LINE       195
 SUB-EXPRESSION (buf_valid[0] | buf_wip[0])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       195
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[1] | buf_wip[1]) & 
      4  (read_buf[1].addr == flash_word_addr) & 
      5  ((~read_buf[1].err)) & 
      6  gen_buf_match[1].part_match & 
      7  gen_buf_match[1].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT1,T2,T3
1011111Not Covered
1101111CoveredT16,T22,T42
1110111CoveredT1,T2,T3
1111011CoveredT33,T62,T214
1111101Not Covered
1111110CoveredT33,T108,T218
1111111CoveredT1,T2,T3

 LINE       195
 SUB-EXPRESSION (buf_valid[1] | buf_wip[1])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       195
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[2] | buf_wip[2]) & 
      4  (read_buf[2].addr == flash_word_addr) & 
      5  ((~read_buf[2].err)) & 
      6  gen_buf_match[2].part_match & 
      7  gen_buf_match[2].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT1,T2,T3
1011111CoveredT153
1101111CoveredT16,T22,T82
1110111CoveredT1,T2,T3
1111011CoveredT62,T214,T212
1111101Not Covered
1111110CoveredT40,T50,T217
1111111CoveredT1,T2,T3

 LINE       195
 SUB-EXPRESSION (buf_valid[2] | buf_wip[2])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       195
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[3] | buf_wip[3]) & 
      4  (read_buf[3].addr == flash_word_addr) & 
      5  ((~read_buf[3].err)) & 
      6  gen_buf_match[3].part_match & 
      7  gen_buf_match[3].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT1,T2,T3
1011111Not Covered
1101111CoveredT16,T22,T82
1110111CoveredT1,T2,T3
1111011CoveredT33,T62,T214
1111101CoveredT215
1111110CoveredT104,T108,T109
1111111CoveredT1,T2,T3

 LINE       195
 SUB-EXPRESSION (buf_valid[3] | buf_wip[3])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       195
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[0].addr == flash_word_addr) & gen_buf_match[0].part_match & gen_buf_match[0].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT33,T167,T112
111CoveredT1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[1].addr == flash_word_addr) & gen_buf_match[1].part_match & gen_buf_match[1].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT33,T126,T108
111CoveredT1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[2].addr == flash_word_addr) & gen_buf_match[2].part_match & gen_buf_match[2].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT40,T50,T217
111CoveredT1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       211
 EXPRESSION ((read_buf[3].addr == flash_word_addr) & gen_buf_match[3].part_match & gen_buf_match[3].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT104,T108,T109
111CoveredT1,T2,T3

 LINE       211
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[0].part_match & 
      3  gen_buf_match[0].info_sel_match)
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT1,T21,T33
111CoveredT1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[1].part_match & 
      3  gen_buf_match[1].info_sel_match)
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT1,T40,T33
111CoveredT1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[2].part_match & 
      3  gen_buf_match[2].info_sel_match)
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT1,T40,T50
111CoveredT1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[3].part_match & 
      3  gen_buf_match[3].info_sel_match)
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT1,T40,T167
111CoveredT1,T2,T3

 LINE       217
 SUB-EXPRESSION (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       221
 EXPRESSION (buf_valid[0] & (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT16,T22,T41
10CoveredT1,T2,T3
11CoveredT16,T22,T82

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT16,T22,T41
010CoveredT16,T11,T82
100CoveredT63,T49,T65

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[0].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T16,T5
11CoveredT16,T11,T82

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[0].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T16,T5
11CoveredT16,T22,T41

 LINE       221
 EXPRESSION (buf_valid[1] & (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT16,T22,T41
10CoveredT1,T2,T3
11CoveredT16,T22,T42

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT16,T22,T41
010CoveredT16,T42,T11
100CoveredT63,T49,T65

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[1].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T16,T5
11CoveredT16,T42,T11

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[1].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T16,T5
11CoveredT16,T22,T41

 LINE       221
 EXPRESSION (buf_valid[2] & (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT16,T22,T41
10CoveredT1,T2,T3
11CoveredT16,T22,T42

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT16,T22,T41
010CoveredT16,T42,T11
100CoveredT63,T49,T65

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[2].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T16,T5
11CoveredT16,T42,T11

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[2].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T16,T5
11CoveredT16,T22,T41

 LINE       221
 EXPRESSION (buf_valid[3] & (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT16,T5,T22
10CoveredT1,T2,T3
11CoveredT16,T5,T22

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT16,T22,T41
010CoveredT16,T5,T42
100CoveredT63,T49,T65

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[3].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T16,T5
11CoveredT16,T5,T42

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[3].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T16,T5
11CoveredT16,T22,T41

 LINE       231
 EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (rdy_o & alloc[0])
             --1--   ----2---
-1--2-StatusTests
01CoveredT5,T33,T63
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       238
 EXPRESSION (rdy_o & alloc[1])
             --1--   ----2---
-1--2-StatusTests
01CoveredT3,T5,T33
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       238
 EXPRESSION (rdy_o & alloc[2])
             --1--   ----2---
-1--2-StatusTests
01CoveredT5,T40,T33
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       238
 EXPRESSION (rdy_o & alloc[3])
             --1--   ----2---
-1--2-StatusTests
01CoveredT3,T5,T40
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       290
 EXPRESSION (req_o & ack_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T63,T50
11CoveredT1,T2,T3

 LINE       291
 EXPRESSION (rd_busy & done_i)
             ---1---   ---2--
-1--2-StatusTests
01CoveredT1,T4,T16
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       301
 EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       304
 EXPRESSION (req_i && rdy_o)
             --1--    --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T5
11CoveredT1,T2,T3

 LINE       307
 EXPRESSION (rsp_fifo_vld & data_valid_o)
             ------1-----   ------2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       376
 EXPRESSION (((~rd_busy)) | rd_done)
             ------1-----   ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       381
 EXPRESSION (rsp_fifo_rdy & scramble_stage_rdy)
             ------1-----   ---------2--------
-1--2-StatusTests
01CoveredT1,T5,T31
10CoveredT13,T14,T36
11CoveredT1,T2,T3

 LINE       392
 EXPRESSION (buf_en_q == buf_en_i)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       398
 EXPRESSION ((no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy) & ((~all_buf_dependency)) & no_buf_en_change & (calc_req_o ? calc_req_done : 1'b1))
             --------------------------------1-------------------------------   -----------2-----------   --------3-------   -----------------4-----------------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Not Covered
1101CoveredT1,T2,T3
1110CoveredT1,T22,T31
1111CoveredT1,T2,T3

 LINE       398
 SUB-EXPRESSION (no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy)
                 ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       398
 SUB-EXPRESSION (ack_i & flash_rdy & rd_stages_rdy)
                 --1--   ----2----   ------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT1,T5,T31
111CoveredT1,T2,T3

 LINE       398
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       406
 EXPRESSION (req_i & no_buf_en_change & flash_rdy & rd_stages_rdy & no_match & (calc_req_o ? calc_req_done : 1'b1))
             --1--   --------2-------   ----3----   ------4------   ----5---   -----------------6-----------------
-1--2--3--4--5--6-StatusTests
011111CoveredT1,T2,T3
101111Not Covered
110111CoveredT3,T31,T39
111011Not Covered
111101CoveredT1,T2,T3
111110CoveredT31,T21,T28
111111CoveredT1,T2,T3

 LINE       406
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       427
 EXPRESSION (rd_done && rd_attrs.ecc)
             ---1---    ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T15
11CoveredT1,T2,T3

 LINE       431
 EXPRESSION (rd_done & (data_i == {flash_phy_pkg::FullDataWidth {1'b1}}))
             ---1---   ------------------------2------------------------
-1--2-StatusTests
01CoveredT1,T16,T5
10CoveredT1,T2,T3
11CoveredT5,T22,T40

 LINE       431
 SUB-EXPRESSION (data_i == {flash_phy_pkg::FullDataWidth {1'b1}})
                ------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T16,T5

 LINE       441
 EXPRESSION (valid_ecc & ecc_multi_err)
             ----1----   ------2------
-1--2-StatusTests
01CoveredT1,T3,T15
10CoveredT1,T2,T3
11CoveredT42,T33,T61

 LINE       450
 EXPRESSION ((data_err | ecc_single_err_o) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
             --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T21,T42

 LINE       450
 SUB-EXPRESSION (data_err | ecc_single_err_o)
                 ----1---   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T21,T33
10CoveredT42,T33,T61

 LINE       455
 EXPRESSION (valid_ecc & ecc_single_err)
             ----1----   -------2------
-1--2-StatusTests
01CoveredT1,T3,T15
10CoveredT1,T2,T3
11CoveredT1,T21,T33

 LINE       488
 EXPRESSION (data_fifo_rdy & mask_fifo_rdy)
             ------1------   ------2------
-1--2-StatusTests
01CoveredT13,T14,T36
10Not Covered
11CoveredT1,T2,T3

 LINE       491
 EXPRESSION (rd_done & rd_attrs.descramble & ((~data_erased)))
             ---1---   ---------2---------   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T3,T4
110CoveredT22,T41,T52
111CoveredT1,T2,T3

 LINE       494
 EXPRESSION (rd_done & rd_attrs.descramble & data_erased)
             ---1---   ---------2---------   -----3-----
-1--2--3-StatusTests
011Not Covered
101CoveredT5,T40,T167
110CoveredT1,T2,T3
111CoveredT22,T41,T52

 LINE       498
 EXPRESSION (rd_done & ((~descram)) & ((~fifo_data_valid)))
             ---1---   ------2-----   ----------3---------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT31,T33,T216
111CoveredT2,T3,T4

 LINE       500
 EXPRESSION (fifo_data_valid & descram_q)
             -------1-------   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T4
11CoveredT1,T2,T3

 LINE       501
 EXPRESSION (fifo_data_valid & dropmsk_q)
             -------1-------   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT22,T41,T52

 LINE       502
 EXPRESSION (fifo_data_valid & forward_q)
             -------1-------   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T3,T4

 LINE       510
 EXPRESSION (hint_descram ? (descramble_req_o & descramble_ack_i) : (hint_dropmsk ? mask_valid : fifo_data_valid))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       510
 SUB-EXPRESSION (descramble_req_o & descramble_ack_i)
                 --------1-------   --------2-------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       510
 SUB-EXPRESSION (hint_dropmsk ? mask_valid : fifo_data_valid)
                 ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT22,T41,T52

 LINE       518
 EXPRESSION (hint_forward & (hint_dropmsk ? mask_valid : 1'b1))
             ------1-----   -----------------2----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT52,T70,T6
11CoveredT2,T3,T4

 LINE       518
 SUB-EXPRESSION (hint_dropmsk ? mask_valid : 1'b1)
                 ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT22,T41,T52

 LINE       520
 EXPRESSION (fifo_data_ready | fifo_forward_pop)
             -------1-------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       574
 EXPRESSION (req_o & ack_i & descramble_i)
             --1--   --2--   ------3-----
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT62,T105,T211
110CoveredT2,T3,T4
111CoveredT1,T2,T3

 LINE       575
 EXPRESSION (calc_req_o & calc_ack_i)
             -----1----   -----2----
-1--2-StatusTests
01CoveredT1,T16,T20
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       591
 EXPRESSION (fifo_data_valid & mask_valid & hint_descram)
             -------1-------   -----2----   ------3-----
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T31,T21
110CoveredT22,T41,T52
111CoveredT1,T2,T3

 LINE       601
 EXPRESSION 
 Number  Term
      1  forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       601
 SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
                 ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       605
 EXPRESSION (forward ? data_err : (((~hint_forward)) ? data_err_q : '0))
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       605
 SUB-EXPRESSION (((~hint_forward)) ? data_err_q : '0)
                 --------1--------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

 LINE       613
 EXPRESSION (forward | (((~hint_forward)) & fifo_data_ready))
             ---1---   ------------------2------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T4

 LINE       613
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       630
 EXPRESSION (forward ? alloc_q : ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0))
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       630
 SUB-EXPRESSION ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0)
                 ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       630
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       635
 EXPRESSION (rsp_fifo_vld & data_valid & (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update)))
             ------1-----   -----2----   --------------------------3-------------------------
-1--2--3-StatusTests
011CoveredT13,T14,T36
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       635
 SUB-EXPRESSION (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update))
                 ------1------   -----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       635
 SUB-EXPRESSION (rsp_fifo_rdata.buf_sel == update)
                -----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       640
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[0] & buf_valid[0])
             ----1---   ------2-----   ------------3------------   ------4-----
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT1,T2,T3
1110CoveredT1,T2,T3
1111CoveredT1,T2,T3

 LINE       640
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[1] & buf_valid[1])
             ----1---   ------2-----   ------------3------------   ------4-----
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT1,T2,T3
1110CoveredT1,T2,T3
1111CoveredT1,T2,T3

 LINE       640
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[2] & buf_valid[2])
             ----1---   ------2-----   ------------3------------   ------4-----
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT1,T2,T3
1110CoveredT1,T2,T3
1111CoveredT1,T2,T3

 LINE       640
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[3] & buf_valid[3])
             ----1---   ------2-----   ------------3------------   ------4-----
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT1,T2,T3
1110CoveredT1,T2,T3
1111CoveredT1,T2,T3

 LINE       651
 EXPRESSION (buf_rsp_err | read_buf[i].err)
             -----1-----   -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT204
10Not Covered

 LINE       657
 EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       670
 EXPRESSION (data_err_o ? ({flash_phy_pkg::BusWidth {1'b1}}) : gen_rd.bus_words_packed[rsp_fifo_rdata.word_sel])
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT42,T33,T10

 LINE       691
 EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       691
 SUB-EXPRESSION (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth])
                ---------------------------------------------1---------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       703
 EXPRESSION (flash_rsp_match | ((|buf_rsp_match)))
             -------1-------   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       706
 EXPRESSION ((data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))) | arb_err_i)
             --------------------------------------1-------------------------------------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT42,T33,T10

 LINE       706
 SUB-EXPRESSION (data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err)))
                 ------1-----   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT42,T33,T10

 LINE       706
 SUB-EXPRESSION (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))
                 ----1----   ----2---   -----------------3----------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010CoveredT1,T2,T3
100CoveredT33,T132,T62
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%