| T1080 |
/workspace/coverage/default/10.flash_ctrl_hw_rma_reset.405864361 |
|
|
Apr 18 01:06:39 PM PDT 24 |
Apr 18 01:20:55 PM PDT 24 |
70135046000 ps |
| T1081 |
/workspace/coverage/default/22.flash_ctrl_smoke.3316511511 |
|
|
Apr 18 01:09:31 PM PDT 24 |
Apr 18 01:12:41 PM PDT 24 |
60862700 ps |
| T1082 |
/workspace/coverage/default/17.flash_ctrl_intr_rd_slow_flash.2462629092 |
|
|
Apr 18 01:08:40 PM PDT 24 |
Apr 18 01:11:48 PM PDT 24 |
8612124600 ps |
| T1083 |
/workspace/coverage/default/10.flash_ctrl_wo.1740119141 |
|
|
Apr 18 01:06:37 PM PDT 24 |
Apr 18 01:09:16 PM PDT 24 |
2826737300 ps |
| T1084 |
/workspace/coverage/default/14.flash_ctrl_otp_reset.2767484841 |
|
|
Apr 18 01:07:46 PM PDT 24 |
Apr 18 01:09:55 PM PDT 24 |
75111300 ps |
| T154 |
/workspace/coverage/default/4.flash_ctrl_host_ctrl_arb.1922644387 |
|
|
Apr 18 01:04:34 PM PDT 24 |
Apr 18 01:37:49 PM PDT 24 |
582611859500 ps |
| T1085 |
/workspace/coverage/default/10.flash_ctrl_re_evict.3981059330 |
|
|
Apr 18 01:06:46 PM PDT 24 |
Apr 18 01:07:20 PM PDT 24 |
268426100 ps |
| T1086 |
/workspace/coverage/default/0.flash_ctrl_sec_info_access.3201603000 |
|
|
Apr 18 01:02:20 PM PDT 24 |
Apr 18 01:03:24 PM PDT 24 |
1837290700 ps |
| T1087 |
/workspace/coverage/default/5.flash_ctrl_intr_rd.2439413257 |
|
|
Apr 18 01:05:07 PM PDT 24 |
Apr 18 01:08:59 PM PDT 24 |
9590704400 ps |
| T1088 |
/workspace/coverage/default/11.flash_ctrl_hw_sec_otp.1187723761 |
|
|
Apr 18 01:06:52 PM PDT 24 |
Apr 18 01:09:07 PM PDT 24 |
10505675900 ps |
| T1089 |
/workspace/coverage/default/42.flash_ctrl_alert_test.1543518361 |
|
|
Apr 18 01:11:38 PM PDT 24 |
Apr 18 01:11:52 PM PDT 24 |
106106400 ps |
| T1090 |
/workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.1441041661 |
|
|
Apr 18 01:06:30 PM PDT 24 |
Apr 18 01:06:44 PM PDT 24 |
21015000 ps |
| T291 |
/workspace/coverage/default/1.flash_ctrl_wr_intg.1591285365 |
|
|
Apr 18 01:02:42 PM PDT 24 |
Apr 18 01:02:57 PM PDT 24 |
47694400 ps |
| T1091 |
/workspace/coverage/default/18.flash_ctrl_disable.3547001937 |
|
|
Apr 18 01:08:50 PM PDT 24 |
Apr 18 01:09:13 PM PDT 24 |
20416200 ps |
| T394 |
/workspace/coverage/default/41.flash_ctrl_sec_info_access.2619600202 |
|
|
Apr 18 01:11:50 PM PDT 24 |
Apr 18 01:12:54 PM PDT 24 |
2638172700 ps |
| T1092 |
/workspace/coverage/default/13.flash_ctrl_lcmgr_intg.3453894168 |
|
|
Apr 18 01:07:37 PM PDT 24 |
Apr 18 01:07:51 PM PDT 24 |
49043000 ps |
| T1093 |
/workspace/coverage/default/12.flash_ctrl_rand_ops.602283937 |
|
|
Apr 18 01:07:07 PM PDT 24 |
Apr 18 01:10:27 PM PDT 24 |
184112800 ps |
| T410 |
/workspace/coverage/default/6.flash_ctrl_rw.3216346774 |
|
|
Apr 18 01:05:27 PM PDT 24 |
Apr 18 01:14:04 PM PDT 24 |
9330682800 ps |
| T1094 |
/workspace/coverage/default/1.flash_ctrl_host_dir_rd.1143799880 |
|
|
Apr 18 01:02:23 PM PDT 24 |
Apr 18 01:04:23 PM PDT 24 |
256014400 ps |
| T1095 |
/workspace/coverage/default/2.flash_ctrl_hw_rma.4188543950 |
|
|
Apr 18 01:03:04 PM PDT 24 |
Apr 18 01:36:28 PM PDT 24 |
338384067500 ps |
| T1096 |
/workspace/coverage/default/66.flash_ctrl_otp_reset.3213807932 |
|
|
Apr 18 01:12:22 PM PDT 24 |
Apr 18 01:14:32 PM PDT 24 |
351618000 ps |
| T1097 |
/workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.4255382869 |
|
|
Apr 18 01:10:17 PM PDT 24 |
Apr 18 01:15:01 PM PDT 24 |
54417629600 ps |
| T1098 |
/workspace/coverage/default/49.flash_ctrl_disable.3607440702 |
|
|
Apr 18 01:12:07 PM PDT 24 |
Apr 18 01:12:29 PM PDT 24 |
10803700 ps |
| T1099 |
/workspace/coverage/default/19.flash_ctrl_smoke.1776557185 |
|
|
Apr 18 01:08:55 PM PDT 24 |
Apr 18 01:11:01 PM PDT 24 |
21383500 ps |
| T1100 |
/workspace/coverage/default/2.flash_ctrl_host_dir_rd.4201076575 |
|
|
Apr 18 01:03:00 PM PDT 24 |
Apr 18 01:04:10 PM PDT 24 |
54401500 ps |
| T1101 |
/workspace/coverage/default/26.flash_ctrl_sec_info_access.3936629639 |
|
|
Apr 18 01:10:02 PM PDT 24 |
Apr 18 01:11:07 PM PDT 24 |
1867881200 ps |
| T1102 |
/workspace/coverage/default/2.flash_ctrl_rand_ops.2720571774 |
|
|
Apr 18 01:02:57 PM PDT 24 |
Apr 18 01:05:58 PM PDT 24 |
62938400 ps |
| T1103 |
/workspace/coverage/default/42.flash_ctrl_connect.1320659494 |
|
|
Apr 18 01:11:36 PM PDT 24 |
Apr 18 01:11:50 PM PDT 24 |
14129800 ps |
| T1104 |
/workspace/coverage/default/31.flash_ctrl_sec_info_access.1494837158 |
|
|
Apr 18 01:10:34 PM PDT 24 |
Apr 18 01:11:32 PM PDT 24 |
1725340100 ps |
| T1105 |
/workspace/coverage/default/18.flash_ctrl_rw_evict_all_en.2698374713 |
|
|
Apr 18 01:08:46 PM PDT 24 |
Apr 18 01:09:15 PM PDT 24 |
45438200 ps |
| T1106 |
/workspace/coverage/default/21.flash_ctrl_alert_test.463754813 |
|
|
Apr 18 01:09:23 PM PDT 24 |
Apr 18 01:09:37 PM PDT 24 |
62013300 ps |
| T1107 |
/workspace/coverage/default/14.flash_ctrl_mp_regions.2556871888 |
|
|
Apr 18 01:07:46 PM PDT 24 |
Apr 18 01:10:07 PM PDT 24 |
19245159700 ps |
| T1108 |
/workspace/coverage/default/7.flash_ctrl_rw_derr.2626616364 |
|
|
Apr 18 01:05:47 PM PDT 24 |
Apr 18 01:13:08 PM PDT 24 |
4385371700 ps |
| T1109 |
/workspace/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.3986232816 |
|
|
Apr 18 01:07:51 PM PDT 24 |
Apr 18 01:10:42 PM PDT 24 |
10019751000 ps |
| T1110 |
/workspace/coverage/default/6.flash_ctrl_connect.3291763206 |
|
|
Apr 18 01:05:36 PM PDT 24 |
Apr 18 01:05:52 PM PDT 24 |
51468600 ps |
| T1111 |
/workspace/coverage/default/4.flash_ctrl_fetch_code.2973190310 |
|
|
Apr 18 01:04:31 PM PDT 24 |
Apr 18 01:04:55 PM PDT 24 |
131404200 ps |
| T1112 |
/workspace/coverage/default/73.flash_ctrl_connect.3477738130 |
|
|
Apr 18 01:12:30 PM PDT 24 |
Apr 18 01:12:44 PM PDT 24 |
16574800 ps |
| T1113 |
/workspace/coverage/default/38.flash_ctrl_otp_reset.1287397489 |
|
|
Apr 18 01:11:13 PM PDT 24 |
Apr 18 01:13:22 PM PDT 24 |
275617000 ps |
| T1114 |
/workspace/coverage/default/19.flash_ctrl_otp_reset.256657493 |
|
|
Apr 18 01:09:03 PM PDT 24 |
Apr 18 01:10:55 PM PDT 24 |
42518400 ps |
| T1115 |
/workspace/coverage/default/10.flash_ctrl_hw_sec_otp.165658127 |
|
|
Apr 18 01:06:37 PM PDT 24 |
Apr 18 01:10:42 PM PDT 24 |
11011113600 ps |
| T1116 |
/workspace/coverage/default/57.flash_ctrl_otp_reset.459641219 |
|
|
Apr 18 01:12:05 PM PDT 24 |
Apr 18 01:14:17 PM PDT 24 |
76805600 ps |
| T413 |
/workspace/coverage/default/0.flash_ctrl_invalid_op.4107433743 |
|
|
Apr 18 01:02:07 PM PDT 24 |
Apr 18 01:03:28 PM PDT 24 |
4073227500 ps |
| T1117 |
/workspace/coverage/default/8.flash_ctrl_mp_regions.2584275139 |
|
|
Apr 18 01:05:57 PM PDT 24 |
Apr 18 01:11:26 PM PDT 24 |
41260711000 ps |
| T395 |
/workspace/coverage/default/23.flash_ctrl_sec_info_access.422825798 |
|
|
Apr 18 01:09:38 PM PDT 24 |
Apr 18 01:10:51 PM PDT 24 |
4392295600 ps |
| T1118 |
/workspace/coverage/default/9.flash_ctrl_rand_ops.323269178 |
|
|
Apr 18 01:06:10 PM PDT 24 |
Apr 18 01:27:27 PM PDT 24 |
6659164700 ps |
| T1119 |
/workspace/coverage/default/13.flash_ctrl_connect.854983560 |
|
|
Apr 18 01:07:36 PM PDT 24 |
Apr 18 01:07:53 PM PDT 24 |
37550000 ps |
| T1120 |
/workspace/coverage/default/19.flash_ctrl_wo.2029332029 |
|
|
Apr 18 01:09:04 PM PDT 24 |
Apr 18 01:11:59 PM PDT 24 |
4011304800 ps |
| T1121 |
/workspace/coverage/default/65.flash_ctrl_otp_reset.599813935 |
|
|
Apr 18 01:12:22 PM PDT 24 |
Apr 18 01:14:11 PM PDT 24 |
38310000 ps |
| T1122 |
/workspace/coverage/default/51.flash_ctrl_otp_reset.3018334886 |
|
|
Apr 18 01:12:07 PM PDT 24 |
Apr 18 01:14:21 PM PDT 24 |
139830700 ps |
| T1123 |
/workspace/coverage/default/13.flash_ctrl_rand_ops.3560852846 |
|
|
Apr 18 01:07:21 PM PDT 24 |
Apr 18 01:12:12 PM PDT 24 |
134493700 ps |
| T1124 |
/workspace/coverage/default/15.flash_ctrl_prog_reset.1189850061 |
|
|
Apr 18 01:07:58 PM PDT 24 |
Apr 18 01:08:12 PM PDT 24 |
34219100 ps |
| T1125 |
/workspace/coverage/default/0.flash_ctrl_config_regwen.687818486 |
|
|
Apr 18 01:02:17 PM PDT 24 |
Apr 18 01:02:31 PM PDT 24 |
228422900 ps |
| T1126 |
/workspace/coverage/default/4.flash_ctrl_read_word_sweep_derr.573244136 |
|
|
Apr 18 01:04:37 PM PDT 24 |
Apr 18 01:05:00 PM PDT 24 |
78010600 ps |
| T1127 |
/workspace/coverage/default/2.flash_ctrl_rw_evict.3551399061 |
|
|
Apr 18 01:03:19 PM PDT 24 |
Apr 18 01:03:55 PM PDT 24 |
584044300 ps |
| T1128 |
/workspace/coverage/default/24.flash_ctrl_intr_rd_slow_flash.196970309 |
|
|
Apr 18 01:09:45 PM PDT 24 |
Apr 18 01:13:15 PM PDT 24 |
16551662700 ps |
| T398 |
/workspace/coverage/default/1.flash_ctrl_sec_info_access.1697480354 |
|
|
Apr 18 01:02:43 PM PDT 24 |
Apr 18 01:03:58 PM PDT 24 |
19580123300 ps |
| T1129 |
/workspace/coverage/default/2.flash_ctrl_intr_wr.917531943 |
|
|
Apr 18 01:03:20 PM PDT 24 |
Apr 18 01:05:01 PM PDT 24 |
8078876200 ps |
| T1130 |
/workspace/coverage/default/19.flash_ctrl_mp_regions.4257720839 |
|
|
Apr 18 01:09:03 PM PDT 24 |
Apr 18 01:13:35 PM PDT 24 |
19485649300 ps |
| T1131 |
/workspace/coverage/default/0.flash_ctrl_rd_intg.2254294763 |
|
|
Apr 18 01:02:16 PM PDT 24 |
Apr 18 01:02:49 PM PDT 24 |
111536400 ps |
| T1132 |
/workspace/coverage/default/9.flash_ctrl_rw_derr.2749448728 |
|
|
Apr 18 01:06:22 PM PDT 24 |
Apr 18 01:14:16 PM PDT 24 |
11175779600 ps |
| T1133 |
/workspace/coverage/default/1.flash_ctrl_stress_all.1307615061 |
|
|
Apr 18 01:02:41 PM PDT 24 |
Apr 18 01:29:33 PM PDT 24 |
1008792000 ps |
| T367 |
/workspace/coverage/default/43.flash_ctrl_disable.1246571737 |
|
|
Apr 18 01:11:38 PM PDT 24 |
Apr 18 01:12:01 PM PDT 24 |
21078100 ps |
| T1134 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3244325298 |
|
|
Apr 18 12:53:52 PM PDT 24 |
Apr 18 12:54:08 PM PDT 24 |
19061500 ps |
| T268 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.1333801374 |
|
|
Apr 18 12:53:56 PM PDT 24 |
Apr 18 12:54:12 PM PDT 24 |
16284400 ps |
| T53 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.701167403 |
|
|
Apr 18 12:53:31 PM PDT 24 |
Apr 18 12:54:17 PM PDT 24 |
40947900 ps |
| T269 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.3576740700 |
|
|
Apr 18 12:54:14 PM PDT 24 |
Apr 18 12:54:28 PM PDT 24 |
45271800 ps |
| T54 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2484412705 |
|
|
Apr 18 12:53:19 PM PDT 24 |
Apr 18 12:53:37 PM PDT 24 |
302413200 ps |
| T317 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.1794663101 |
|
|
Apr 18 12:53:33 PM PDT 24 |
Apr 18 12:53:47 PM PDT 24 |
17525800 ps |
| T1135 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.956294434 |
|
|
Apr 18 12:53:17 PM PDT 24 |
Apr 18 12:53:33 PM PDT 24 |
14427700 ps |
| T55 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.285339454 |
|
|
Apr 18 12:54:20 PM PDT 24 |
Apr 18 12:54:39 PM PDT 24 |
919798100 ps |
| T192 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.1032649011 |
|
|
Apr 18 12:53:34 PM PDT 24 |
Apr 18 12:54:19 PM PDT 24 |
8233148100 ps |
| T318 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.1640564984 |
|
|
Apr 18 12:54:31 PM PDT 24 |
Apr 18 12:54:46 PM PDT 24 |
69565700 ps |
| T1136 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.223866324 |
|
|
Apr 18 12:54:36 PM PDT 24 |
Apr 18 12:54:53 PM PDT 24 |
11718900 ps |
| T261 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1965321247 |
|
|
Apr 18 12:52:49 PM PDT 24 |
Apr 18 12:53:21 PM PDT 24 |
59996300 ps |
| T1137 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.4152376005 |
|
|
Apr 18 12:53:16 PM PDT 24 |
Apr 18 12:53:32 PM PDT 24 |
49922400 ps |
| T319 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.23027276 |
|
|
Apr 18 12:54:43 PM PDT 24 |
Apr 18 12:54:57 PM PDT 24 |
14699300 ps |
| T193 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.3978051172 |
|
|
Apr 18 12:54:01 PM PDT 24 |
Apr 18 12:54:19 PM PDT 24 |
70792900 ps |
| T262 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.2113742356 |
|
|
Apr 18 12:53:00 PM PDT 24 |
Apr 18 12:53:42 PM PDT 24 |
1163634000 ps |
| T1138 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.2017503159 |
|
|
Apr 18 12:53:46 PM PDT 24 |
Apr 18 12:54:02 PM PDT 24 |
99875800 ps |
| T194 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.1725992868 |
|
|
Apr 18 12:54:20 PM PDT 24 |
Apr 18 01:01:56 PM PDT 24 |
1433754700 ps |
| T219 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.201373341 |
|
|
Apr 18 12:53:38 PM PDT 24 |
Apr 18 12:53:55 PM PDT 24 |
40299300 ps |
| T220 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.371433723 |
|
|
Apr 18 12:53:38 PM PDT 24 |
Apr 18 01:01:17 PM PDT 24 |
423084100 ps |
| T1139 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.2096536765 |
|
|
Apr 18 12:54:26 PM PDT 24 |
Apr 18 12:54:40 PM PDT 24 |
17184000 ps |
| T322 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.2074516049 |
|
|
Apr 18 12:54:43 PM PDT 24 |
Apr 18 12:54:59 PM PDT 24 |
15929500 ps |
| T254 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1551497111 |
|
|
Apr 18 12:52:59 PM PDT 24 |
Apr 18 12:53:16 PM PDT 24 |
72585800 ps |
| T255 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.4161023822 |
|
|
Apr 18 12:53:16 PM PDT 24 |
Apr 18 12:53:32 PM PDT 24 |
107290300 ps |
| T221 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.900886686 |
|
|
Apr 18 12:54:27 PM PDT 24 |
Apr 18 12:54:46 PM PDT 24 |
192080300 ps |
| T238 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.2848674119 |
|
|
Apr 18 12:54:23 PM PDT 24 |
Apr 18 12:54:41 PM PDT 24 |
462216200 ps |
| T263 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.531008927 |
|
|
Apr 18 12:53:25 PM PDT 24 |
Apr 18 12:54:03 PM PDT 24 |
96343000 ps |
| T222 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.543509444 |
|
|
Apr 18 12:53:05 PM PDT 24 |
Apr 18 01:00:36 PM PDT 24 |
410982400 ps |
| T239 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.927194831 |
|
|
Apr 18 12:53:23 PM PDT 24 |
Apr 18 12:53:41 PM PDT 24 |
222606600 ps |
| T320 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.2007221166 |
|
|
Apr 18 12:54:35 PM PDT 24 |
Apr 18 12:54:50 PM PDT 24 |
30377100 ps |
| T256 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.653468746 |
|
|
Apr 18 12:53:22 PM PDT 24 |
Apr 18 12:53:41 PM PDT 24 |
818494400 ps |
| T321 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1661066605 |
|
|
Apr 18 12:54:36 PM PDT 24 |
Apr 18 12:54:51 PM PDT 24 |
45730300 ps |
| T223 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.3341999166 |
|
|
Apr 18 12:54:12 PM PDT 24 |
Apr 18 01:06:47 PM PDT 24 |
5362796000 ps |
| T1140 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3394344134 |
|
|
Apr 18 12:53:57 PM PDT 24 |
Apr 18 12:54:14 PM PDT 24 |
19993600 ps |
| T1141 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3572820679 |
|
|
Apr 18 12:53:36 PM PDT 24 |
Apr 18 12:53:50 PM PDT 24 |
13008600 ps |
| T242 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.3165635683 |
|
|
Apr 18 12:53:21 PM PDT 24 |
Apr 18 01:08:21 PM PDT 24 |
881523800 ps |
| T240 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.3650039236 |
|
|
Apr 18 12:54:07 PM PDT 24 |
Apr 18 12:54:22 PM PDT 24 |
89673000 ps |
| T332 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.1774675928 |
|
|
Apr 18 12:54:35 PM PDT 24 |
Apr 18 12:54:51 PM PDT 24 |
56083400 ps |
| T224 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.4016819028 |
|
|
Apr 18 12:52:59 PM PDT 24 |
Apr 18 01:00:32 PM PDT 24 |
210055700 ps |
| T241 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.3461271872 |
|
|
Apr 18 12:54:08 PM PDT 24 |
Apr 18 12:54:25 PM PDT 24 |
123607400 ps |
| T1142 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.3522944035 |
|
|
Apr 18 12:53:51 PM PDT 24 |
Apr 18 12:54:05 PM PDT 24 |
55587300 ps |
| T243 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.235223691 |
|
|
Apr 18 12:53:38 PM PDT 24 |
Apr 18 12:53:55 PM PDT 24 |
402712800 ps |
| T351 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.3974042915 |
|
|
Apr 18 12:54:37 PM PDT 24 |
Apr 18 12:54:51 PM PDT 24 |
15346600 ps |
| T257 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.4123212031 |
|
|
Apr 18 12:53:47 PM PDT 24 |
Apr 18 12:54:04 PM PDT 24 |
72359000 ps |
| T293 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.714580140 |
|
|
Apr 18 12:54:14 PM PDT 24 |
Apr 18 12:54:31 PM PDT 24 |
248392300 ps |
| T1143 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.279171322 |
|
|
Apr 18 12:53:55 PM PDT 24 |
Apr 18 12:54:11 PM PDT 24 |
40660500 ps |
| T1144 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.2194763337 |
|
|
Apr 18 12:53:32 PM PDT 24 |
Apr 18 12:53:46 PM PDT 24 |
47337200 ps |
| T1145 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.2057433217 |
|
|
Apr 18 12:53:50 PM PDT 24 |
Apr 18 12:54:07 PM PDT 24 |
12343100 ps |
| T1146 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.2629389276 |
|
|
Apr 18 12:54:12 PM PDT 24 |
Apr 18 12:54:27 PM PDT 24 |
20797300 ps |
| T244 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3707269622 |
|
|
Apr 18 12:53:56 PM PDT 24 |
Apr 18 12:54:17 PM PDT 24 |
103247700 ps |
| T264 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.3463502090 |
|
|
Apr 18 12:54:27 PM PDT 24 |
Apr 18 12:54:43 PM PDT 24 |
36666100 ps |
| T1147 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.2621159552 |
|
|
Apr 18 12:53:04 PM PDT 24 |
Apr 18 12:53:18 PM PDT 24 |
32932800 ps |
| T1148 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1009631127 |
|
|
Apr 18 12:52:55 PM PDT 24 |
Apr 18 12:53:47 PM PDT 24 |
1752064500 ps |
| T1149 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.772804169 |
|
|
Apr 18 12:54:33 PM PDT 24 |
Apr 18 12:55:07 PM PDT 24 |
474352500 ps |
| T1150 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.820186529 |
|
|
Apr 18 12:53:56 PM PDT 24 |
Apr 18 12:54:13 PM PDT 24 |
11787700 ps |
| T315 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1453103316 |
|
|
Apr 18 12:54:33 PM PDT 24 |
Apr 18 12:54:52 PM PDT 24 |
52239300 ps |
| T353 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.1260486004 |
|
|
Apr 18 12:54:27 PM PDT 24 |
Apr 18 01:02:08 PM PDT 24 |
450472300 ps |
| T1151 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.3827569339 |
|
|
Apr 18 12:54:27 PM PDT 24 |
Apr 18 12:54:42 PM PDT 24 |
201084400 ps |
| T1152 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.3228351015 |
|
|
Apr 18 12:52:53 PM PDT 24 |
Apr 18 12:53:10 PM PDT 24 |
35192800 ps |
| T1153 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.170403013 |
|
|
Apr 18 12:53:08 PM PDT 24 |
Apr 18 12:53:22 PM PDT 24 |
58018300 ps |
| T294 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.1692470926 |
|
|
Apr 18 12:54:32 PM PDT 24 |
Apr 18 12:54:51 PM PDT 24 |
76494200 ps |
| T1154 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2977160052 |
|
|
Apr 18 12:52:54 PM PDT 24 |
Apr 18 12:53:10 PM PDT 24 |
16708500 ps |
| T1155 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.921777238 |
|
|
Apr 18 12:53:04 PM PDT 24 |
Apr 18 12:53:17 PM PDT 24 |
27263800 ps |
| T355 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1936934251 |
|
|
Apr 18 12:54:08 PM PDT 24 |
Apr 18 01:01:56 PM PDT 24 |
1315708400 ps |
| T1156 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.3857328574 |
|
|
Apr 18 12:52:49 PM PDT 24 |
Apr 18 12:53:02 PM PDT 24 |
15933900 ps |
| T265 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2677837045 |
|
|
Apr 18 12:53:39 PM PDT 24 |
Apr 18 12:54:00 PM PDT 24 |
232300700 ps |
| T1157 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.606722586 |
|
|
Apr 18 12:54:46 PM PDT 24 |
Apr 18 12:55:01 PM PDT 24 |
16013700 ps |
| T1158 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.2466029791 |
|
|
Apr 18 12:54:14 PM PDT 24 |
Apr 18 12:54:31 PM PDT 24 |
68253300 ps |
| T272 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.4077992236 |
|
|
Apr 18 12:54:14 PM PDT 24 |
Apr 18 12:54:30 PM PDT 24 |
59497400 ps |
| T1159 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.2154501112 |
|
|
Apr 18 12:52:50 PM PDT 24 |
Apr 18 12:53:04 PM PDT 24 |
53161100 ps |
| T1160 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.3333532553 |
|
|
Apr 18 12:52:49 PM PDT 24 |
Apr 18 12:53:05 PM PDT 24 |
11820100 ps |
| T271 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.1548516541 |
|
|
Apr 18 12:54:12 PM PDT 24 |
Apr 18 12:54:33 PM PDT 24 |
204164900 ps |
| T1161 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.200311018 |
|
|
Apr 18 12:54:27 PM PDT 24 |
Apr 18 12:54:44 PM PDT 24 |
15038300 ps |
| T1162 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.2796325010 |
|
|
Apr 18 12:53:12 PM PDT 24 |
Apr 18 12:54:35 PM PDT 24 |
9568484200 ps |
| T1163 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.1366538074 |
|
|
Apr 18 12:54:43 PM PDT 24 |
Apr 18 12:54:59 PM PDT 24 |
182833700 ps |
| T1164 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2916432649 |
|
|
Apr 18 12:53:39 PM PDT 24 |
Apr 18 12:53:55 PM PDT 24 |
19251600 ps |
| T266 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1369685180 |
|
|
Apr 18 12:53:17 PM PDT 24 |
Apr 18 12:53:37 PM PDT 24 |
208481700 ps |
| T1165 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.412270997 |
|
|
Apr 18 12:53:00 PM PDT 24 |
Apr 18 12:53:16 PM PDT 24 |
328377700 ps |
| T1166 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.618653177 |
|
|
Apr 18 12:54:37 PM PDT 24 |
Apr 18 12:54:51 PM PDT 24 |
62863700 ps |
| T1167 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.2074776423 |
|
|
Apr 18 12:53:56 PM PDT 24 |
Apr 18 12:54:15 PM PDT 24 |
275730800 ps |
| T267 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.488551883 |
|
|
Apr 18 12:53:33 PM PDT 24 |
Apr 18 12:53:52 PM PDT 24 |
93924000 ps |
| T1168 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2312610424 |
|
|
Apr 18 12:53:49 PM PDT 24 |
Apr 18 12:54:05 PM PDT 24 |
15072500 ps |
| T1169 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.714932824 |
|
|
Apr 18 12:54:18 PM PDT 24 |
Apr 18 12:54:33 PM PDT 24 |
62421800 ps |
| T1170 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.1314224204 |
|
|
Apr 18 12:54:35 PM PDT 24 |
Apr 18 12:54:50 PM PDT 24 |
28517400 ps |
| T273 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2908990334 |
|
|
Apr 18 12:53:21 PM PDT 24 |
Apr 18 12:53:40 PM PDT 24 |
118750000 ps |
| T1171 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.2666501520 |
|
|
Apr 18 12:53:11 PM PDT 24 |
Apr 18 12:53:24 PM PDT 24 |
68357500 ps |
| T1172 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.1980239912 |
|
|
Apr 18 12:53:17 PM PDT 24 |
Apr 18 12:53:31 PM PDT 24 |
17868800 ps |
| T1173 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.3977204488 |
|
|
Apr 18 12:54:31 PM PDT 24 |
Apr 18 12:54:46 PM PDT 24 |
47782100 ps |
| T1174 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.1822469554 |
|
|
Apr 18 12:53:45 PM PDT 24 |
Apr 18 12:54:00 PM PDT 24 |
53600800 ps |
| T1175 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.3237055886 |
|
|
Apr 18 12:53:23 PM PDT 24 |
Apr 18 12:53:39 PM PDT 24 |
20629400 ps |
| T274 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.1293642417 |
|
|
Apr 18 12:53:02 PM PDT 24 |
Apr 18 12:53:22 PM PDT 24 |
312374200 ps |
| T1176 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1538898503 |
|
|
Apr 18 12:54:20 PM PDT 24 |
Apr 18 12:54:36 PM PDT 24 |
28762700 ps |
| T295 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2317248689 |
|
|
Apr 18 12:53:02 PM PDT 24 |
Apr 18 12:54:03 PM PDT 24 |
3000264300 ps |
| T1177 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.2791121509 |
|
|
Apr 18 12:54:32 PM PDT 24 |
Apr 18 12:54:49 PM PDT 24 |
29034200 ps |
| T245 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.2943674011 |
|
|
Apr 18 12:53:10 PM PDT 24 |
Apr 18 12:53:24 PM PDT 24 |
31195200 ps |
| T296 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.3395977170 |
|
|
Apr 18 12:53:44 PM PDT 24 |
Apr 18 12:54:02 PM PDT 24 |
190133100 ps |
| T297 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.2779902489 |
|
|
Apr 18 12:54:32 PM PDT 24 |
Apr 18 12:54:55 PM PDT 24 |
1224640000 ps |
| T1178 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.250828383 |
|
|
Apr 18 12:53:50 PM PDT 24 |
Apr 18 12:54:04 PM PDT 24 |
49881900 ps |
| T1179 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.2362158144 |
|
|
Apr 18 12:53:44 PM PDT 24 |
Apr 18 12:54:18 PM PDT 24 |
111027500 ps |
| T1180 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.852076078 |
|
|
Apr 18 12:53:40 PM PDT 24 |
Apr 18 12:53:56 PM PDT 24 |
208945600 ps |
| T1181 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.377646209 |
|
|
Apr 18 12:54:45 PM PDT 24 |
Apr 18 12:55:00 PM PDT 24 |
52320200 ps |
| T1182 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.1321472414 |
|
|
Apr 18 12:54:31 PM PDT 24 |
Apr 18 12:54:46 PM PDT 24 |
42144700 ps |
| T1183 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.3251177071 |
|
|
Apr 18 12:53:33 PM PDT 24 |
Apr 18 12:53:52 PM PDT 24 |
120895400 ps |
| T1184 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.1578907726 |
|
|
Apr 18 12:53:41 PM PDT 24 |
Apr 18 12:53:55 PM PDT 24 |
37901700 ps |
| T1185 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.2068047309 |
|
|
Apr 18 12:53:51 PM PDT 24 |
Apr 18 12:54:25 PM PDT 24 |
411739600 ps |
| T1186 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2927476224 |
|
|
Apr 18 12:52:49 PM PDT 24 |
Apr 18 12:53:06 PM PDT 24 |
82489400 ps |
| T1187 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.3241210804 |
|
|
Apr 18 12:54:06 PM PDT 24 |
Apr 18 12:54:20 PM PDT 24 |
20139100 ps |
| T1188 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.2988690130 |
|
|
Apr 18 12:54:35 PM PDT 24 |
Apr 18 12:54:51 PM PDT 24 |
97013700 ps |
| T1189 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.2112523586 |
|
|
Apr 18 12:52:53 PM PDT 24 |
Apr 18 12:53:13 PM PDT 24 |
342606100 ps |
| T1190 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2418276304 |
|
|
Apr 18 12:54:13 PM PDT 24 |
Apr 18 12:54:30 PM PDT 24 |
73269300 ps |
| T1191 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.2013346267 |
|
|
Apr 18 12:54:08 PM PDT 24 |
Apr 18 12:54:42 PM PDT 24 |
607475000 ps |
| T1192 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.572100801 |
|
|
Apr 18 12:54:43 PM PDT 24 |
Apr 18 12:54:58 PM PDT 24 |
31667400 ps |
| T1193 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.3306831224 |
|
|
Apr 18 12:53:39 PM PDT 24 |
Apr 18 12:53:56 PM PDT 24 |
13778700 ps |
| T1194 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.3872984805 |
|
|
Apr 18 12:54:13 PM PDT 24 |
Apr 18 12:54:28 PM PDT 24 |
28248400 ps |
| T246 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.3870608427 |
|
|
Apr 18 12:52:48 PM PDT 24 |
Apr 18 12:53:02 PM PDT 24 |
16865900 ps |
| T1195 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.3030216500 |
|
|
Apr 18 12:53:32 PM PDT 24 |
Apr 18 12:53:49 PM PDT 24 |
179048200 ps |
| T1196 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2275231109 |
|
|
Apr 18 12:53:21 PM PDT 24 |
Apr 18 12:53:38 PM PDT 24 |
19989300 ps |
| T1197 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.337043414 |
|
|
Apr 18 12:54:36 PM PDT 24 |
Apr 18 12:54:51 PM PDT 24 |
80664000 ps |
| T1198 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.3964765295 |
|
|
Apr 18 12:54:12 PM PDT 24 |
Apr 18 12:54:31 PM PDT 24 |
95670600 ps |
| T357 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.2299674138 |
|
|
Apr 18 12:53:57 PM PDT 24 |
Apr 18 01:00:24 PM PDT 24 |
355446900 ps |
| T1199 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2208036748 |
|
|
Apr 18 12:54:30 PM PDT 24 |
Apr 18 12:54:49 PM PDT 24 |
27963500 ps |
| T1200 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.512276074 |
|
|
Apr 18 12:53:50 PM PDT 24 |
Apr 18 12:54:07 PM PDT 24 |
26721600 ps |
| T1201 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.3806777394 |
|
|
Apr 18 12:54:18 PM PDT 24 |
Apr 18 12:54:34 PM PDT 24 |
11434500 ps |
| T1202 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2147130924 |
|
|
Apr 18 12:54:19 PM PDT 24 |
Apr 18 12:54:34 PM PDT 24 |
117153300 ps |
| T247 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1060194020 |
|
|
Apr 18 12:53:20 PM PDT 24 |
Apr 18 12:53:33 PM PDT 24 |
61299300 ps |
| T1203 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3620632666 |
|
|
Apr 18 12:52:55 PM PDT 24 |
Apr 18 12:53:13 PM PDT 24 |
64442000 ps |
| T1204 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.2091446078 |
|
|
Apr 18 12:53:45 PM PDT 24 |
Apr 18 12:53:59 PM PDT 24 |
29743300 ps |
| T1205 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.1637173797 |
|
|
Apr 18 12:54:13 PM PDT 24 |
Apr 18 12:54:30 PM PDT 24 |
45360300 ps |
| T1206 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.3015760616 |
|
|
Apr 18 12:54:33 PM PDT 24 |
Apr 18 12:54:48 PM PDT 24 |
30314300 ps |
| T352 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.4272854777 |
|
|
Apr 18 12:54:07 PM PDT 24 |
Apr 18 12:54:24 PM PDT 24 |
32981000 ps |
| T1207 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.1561418479 |
|
|
Apr 18 12:54:32 PM PDT 24 |
Apr 18 12:54:50 PM PDT 24 |
12447000 ps |
| T1208 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1980402820 |
|
|
Apr 18 12:54:13 PM PDT 24 |
Apr 18 12:54:27 PM PDT 24 |
14937400 ps |
| T1209 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.2206706471 |
|
|
Apr 18 12:54:35 PM PDT 24 |
Apr 18 12:54:50 PM PDT 24 |
14980000 ps |
| T1210 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.604634928 |
|
|
Apr 18 12:54:12 PM PDT 24 |
Apr 18 12:54:28 PM PDT 24 |
22302700 ps |
| T356 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3726662996 |
|
|
Apr 18 12:54:31 PM PDT 24 |
Apr 18 01:07:10 PM PDT 24 |
346159500 ps |
| T354 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3482079871 |
|
|
Apr 18 12:53:39 PM PDT 24 |
Apr 18 01:00:05 PM PDT 24 |
690991100 ps |
| T1211 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.654519354 |
|
|
Apr 18 12:53:44 PM PDT 24 |
Apr 18 01:01:32 PM PDT 24 |
713053700 ps |
| T1212 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.392045873 |
|
|
Apr 18 12:54:07 PM PDT 24 |
Apr 18 12:54:25 PM PDT 24 |
130461100 ps |
| T1213 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.3305925094 |
|
|
Apr 18 12:53:40 PM PDT 24 |
Apr 18 12:53:57 PM PDT 24 |
106668800 ps |
| T1214 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.4057704267 |
|
|
Apr 18 12:54:32 PM PDT 24 |
Apr 18 12:54:50 PM PDT 24 |
185026300 ps |
| T362 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.818618068 |
|
|
Apr 18 12:54:31 PM PDT 24 |
Apr 18 01:09:24 PM PDT 24 |
346339000 ps |
| T1215 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3041476031 |
|
|
Apr 18 12:52:53 PM PDT 24 |
Apr 18 12:53:07 PM PDT 24 |
39528400 ps |
| T1216 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.1246230922 |
|
|
Apr 18 12:54:20 PM PDT 24 |
Apr 18 12:54:35 PM PDT 24 |
53604200 ps |
| T1217 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.3679086830 |
|
|
Apr 18 12:53:33 PM PDT 24 |
Apr 18 12:53:49 PM PDT 24 |
215142400 ps |
| T1218 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.3411758629 |
|
|
Apr 18 12:53:51 PM PDT 24 |
Apr 18 12:54:06 PM PDT 24 |
196885900 ps |
| T1219 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.2754300822 |
|
|
Apr 18 12:54:35 PM PDT 24 |
Apr 18 12:54:50 PM PDT 24 |
87446500 ps |
| T1220 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.3496696522 |
|
|
Apr 18 12:54:19 PM PDT 24 |
Apr 18 12:54:33 PM PDT 24 |
62943500 ps |
| T1221 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.2098141209 |
|
|
Apr 18 12:53:33 PM PDT 24 |
Apr 18 12:53:50 PM PDT 24 |
148866500 ps |
| T1222 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.4201565667 |
|
|
Apr 18 12:54:31 PM PDT 24 |
Apr 18 12:54:48 PM PDT 24 |
11674400 ps |
| T298 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.87675758 |
|
|
Apr 18 12:54:07 PM PDT 24 |
Apr 18 12:54:26 PM PDT 24 |
204766400 ps |
| T1223 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.4183488865 |
|
|
Apr 18 12:52:54 PM PDT 24 |
Apr 18 12:53:14 PM PDT 24 |
241439700 ps |
| T1224 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.2491833315 |
|
|
Apr 18 12:54:36 PM PDT 24 |
Apr 18 12:54:51 PM PDT 24 |
35327000 ps |
| T1225 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.1180562125 |
|
|
Apr 18 12:54:30 PM PDT 24 |
Apr 18 12:54:44 PM PDT 24 |
36392700 ps |
| T1226 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.845323955 |
|
|
Apr 18 12:53:53 PM PDT 24 |
Apr 18 12:54:07 PM PDT 24 |
20641800 ps |
| T1227 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.2203104326 |
|
|
Apr 18 12:53:21 PM PDT 24 |
Apr 18 12:54:35 PM PDT 24 |
2916401500 ps |
| T248 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1808934798 |
|
|
Apr 18 12:53:30 PM PDT 24 |
Apr 18 12:53:44 PM PDT 24 |
57386000 ps |
| T1228 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2798325096 |
|
|
Apr 18 12:53:46 PM PDT 24 |
Apr 18 12:54:03 PM PDT 24 |
40102500 ps |
| T1229 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.3320357119 |
|
|
Apr 18 12:53:52 PM PDT 24 |
Apr 18 12:54:09 PM PDT 24 |
102878700 ps |
| T360 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.2111737750 |
|
|
Apr 18 12:53:53 PM PDT 24 |
Apr 18 01:06:43 PM PDT 24 |
665731400 ps |
| T1230 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.3609751618 |
|
|
Apr 18 12:52:59 PM PDT 24 |
Apr 18 12:53:13 PM PDT 24 |
39869600 ps |
| T1231 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.2384000286 |
|
|
Apr 18 12:53:44 PM PDT 24 |
Apr 18 12:54:04 PM PDT 24 |
224671500 ps |
| T1232 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3923706636 |
|
|
Apr 18 12:53:57 PM PDT 24 |
Apr 18 12:54:14 PM PDT 24 |
154059700 ps |
| T1233 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.1717208546 |
|
|
Apr 18 12:54:35 PM PDT 24 |
Apr 18 12:54:51 PM PDT 24 |
16399200 ps |
| T361 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.1852736347 |
|
|
Apr 18 12:52:59 PM PDT 24 |
Apr 18 01:05:28 PM PDT 24 |
1314329400 ps |
| T1234 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.823406929 |
|
|
Apr 18 12:53:18 PM PDT 24 |
Apr 18 12:54:07 PM PDT 24 |
4015764500 ps |
| T1235 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.3081674590 |
|
|
Apr 18 12:53:30 PM PDT 24 |
Apr 18 12:53:43 PM PDT 24 |
25447500 ps |
| T1236 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.2339042021 |
|
|
Apr 18 12:53:27 PM PDT 24 |
Apr 18 12:53:41 PM PDT 24 |
28040500 ps |
| T1237 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.1398948703 |
|
|
Apr 18 12:52:54 PM PDT 24 |
Apr 18 12:53:08 PM PDT 24 |
92914800 ps |
| T1238 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.1506281782 |
|
|
Apr 18 12:53:39 PM PDT 24 |
Apr 18 12:53:58 PM PDT 24 |
58391100 ps |
| T358 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.2770840396 |
|
|
Apr 18 12:53:17 PM PDT 24 |
Apr 18 01:00:52 PM PDT 24 |
178131400 ps |
| T1239 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3788257280 |
|
|
Apr 18 12:52:48 PM PDT 24 |
Apr 18 12:53:07 PM PDT 24 |
54208000 ps |
| T359 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2368910407 |
|
|
Apr 18 12:54:03 PM PDT 24 |
Apr 18 01:08:57 PM PDT 24 |
1455510300 ps |
| T1240 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.236494304 |
|
|
Apr 18 12:53:38 PM PDT 24 |
Apr 18 12:53:54 PM PDT 24 |
336206700 ps |
| T1241 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.633152602 |
|
|
Apr 18 12:53:58 PM PDT 24 |
Apr 18 12:54:13 PM PDT 24 |
70172600 ps |
| T1242 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.4062541544 |
|
|
Apr 18 12:54:43 PM PDT 24 |
Apr 18 12:54:58 PM PDT 24 |
29215600 ps |
| T1243 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.697247978 |
|
|
Apr 18 12:53:44 PM PDT 24 |
Apr 18 12:54:01 PM PDT 24 |
13133100 ps |
| T1244 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.742074871 |
|
|
Apr 18 12:53:50 PM PDT 24 |
Apr 18 12:54:08 PM PDT 24 |
153685700 ps |
| T1245 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.3424981279 |
|
|
Apr 18 12:54:44 PM PDT 24 |
Apr 18 12:54:59 PM PDT 24 |
32301200 ps |
| T1246 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.3015786325 |
|
|
Apr 18 12:53:34 PM PDT 24 |
Apr 18 01:08:25 PM PDT 24 |
3403479900 ps |
| T249 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1651149374 |
|
|
Apr 18 12:52:59 PM PDT 24 |
Apr 18 12:53:13 PM PDT 24 |
17232000 ps |
| T270 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.424464420 |
|
|
Apr 18 12:53:51 PM PDT 24 |
Apr 18 01:01:22 PM PDT 24 |
2112945900 ps |
| T1247 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.190676748 |
|
|
Apr 18 12:53:18 PM PDT 24 |
Apr 18 12:53:32 PM PDT 24 |
35422400 ps |
| T1248 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.1548811706 |
|
|
Apr 18 12:53:13 PM PDT 24 |
Apr 18 12:53:58 PM PDT 24 |
179578200 ps |
| T1249 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3751414942 |
|
|
Apr 18 12:52:58 PM PDT 24 |
Apr 18 12:53:17 PM PDT 24 |
300540300 ps |
| T1250 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.720315472 |
|
|
Apr 18 12:54:25 PM PDT 24 |
Apr 18 12:54:41 PM PDT 24 |
21819200 ps |
| T1251 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.459462594 |
|
|
Apr 18 12:54:37 PM PDT 24 |
Apr 18 12:54:51 PM PDT 24 |
54576600 ps |
| T1252 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2709401295 |
|
|
Apr 18 12:53:29 PM PDT 24 |
Apr 18 12:53:43 PM PDT 24 |
15849100 ps |
| T1253 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1345973451 |
|
|
Apr 18 12:54:32 PM PDT 24 |
Apr 18 12:54:47 PM PDT 24 |
45953400 ps |