Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	321819	1		T1	1		T2	1		T3	1175
all_values[1]	321819	1		T1	1		T2	1		T3	1175
all_values[2]	321819	1		T1	1		T2	1		T3	1175
all_values[3]	321819	1		T1	1		T2	1		T3	1175
all_values[4]	321819	1		T1	1		T2	1		T3	1175
all_values[5]	321819	1		T1	1		T2	1		T3	1175

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	650050	1		T1	6		T2	6		T3	2350
auto[1]	1280864	1		T3	4700		T8	21772		T24	7848

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	943637	1		T1	4		T2	4		T3	3526
auto[1]	987277	1		T1	2		T2	2		T3	3524

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	321673	1		T1	1		T2	1		T3	1175
all_values[0]	auto[1]	auto[1]	146	1		T265	3		T266	4		T267	1
all_values[1]	auto[0]	auto[1]	321646	1		T1	1		T2	1		T3	1175
all_values[1]	auto[1]	auto[1]	173	1		T265	2		T266	4		T267	4
all_values[2]	auto[0]	auto[0]	1612	1		T1	1		T2	1		T4	2
all_values[2]	auto[0]	auto[1]	59	1		T265	2		T266	1		T267	1
all_values[2]	auto[1]	auto[0]	320090	1		T3	1175		T8	5443		T24	1962
all_values[2]	auto[1]	auto[1]	58	1		T267	1		T323	1		T322	2
all_values[3]	auto[0]	auto[0]	1634	1		T1	1		T2	1		T4	2
all_values[3]	auto[0]	auto[1]	62	1		T265	3		T321	1		T323	1
all_values[3]	auto[1]	auto[0]	75070	1		T3	1175		T8	238		T24	980
all_values[3]	auto[1]	auto[1]	245053	1		T8	5205		T24	982		T7	897
all_values[4]	auto[0]	auto[0]	1150	1		T1	1		T2	1		T4	1
all_values[4]	auto[0]	auto[1]	532	1		T4	1		T5	1		T16	1
all_values[4]	auto[1]	auto[0]	222480	1		T3	1		T8	4413		T24	980
all_values[4]	auto[1]	auto[1]	97657	1		T3	1174		T8	1030		T24	982
all_values[5]	auto[0]	auto[0]	1540	1		T1	1		T2	1		T4	2
all_values[5]	auto[0]	auto[1]	142	1		T5	1		T33	1		T34	1
all_values[5]	auto[1]	auto[0]	320061	1		T3	1175		T8	5443		T24	1962
all_values[5]	auto[1]	auto[1]	76	1		T265	3		T267	1		T321	2