Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T112 |
8 |
|
T114 |
3 |
|
T210 |
1 |
| others[1] |
202 |
1 |
|
T118 |
1 |
|
T61 |
1 |
|
T112 |
8 |
| others[2] |
223 |
1 |
|
T16 |
1 |
|
T112 |
9 |
|
T114 |
15 |
| others[3] |
365 |
1 |
|
T5 |
1 |
|
T41 |
1 |
|
T110 |
1 |
| false |
121 |
1 |
|
T41 |
1 |
|
T128 |
1 |
|
T112 |
5 |
| true |
12412 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
7918 |
1 |
|
T9 |
1 |
|
T17 |
1 |
|
T60 |
2 |
| others[1] |
1281 |
1 |
|
T4 |
4 |
|
T99 |
20 |
|
T67 |
3 |
| others[2] |
1260 |
1 |
|
T4 |
1 |
|
T9 |
1 |
|
T99 |
17 |
| others[3] |
2056 |
1 |
|
T4 |
6 |
|
T16 |
1 |
|
T9 |
3 |
| false |
606 |
1 |
|
T3 |
1 |
|
T9 |
2 |
|
T99 |
14 |
| true |
433 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
7883 |
1 |
|
T4 |
1 |
|
T9 |
3 |
|
T17 |
1 |
| others[1] |
1249 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T9 |
1 |
| others[2] |
1255 |
1 |
|
T4 |
2 |
|
T9 |
1 |
|
T178 |
1 |
| others[3] |
2083 |
1 |
|
T4 |
5 |
|
T9 |
2 |
|
T24 |
1 |
| false |
667 |
1 |
|
T4 |
2 |
|
T16 |
1 |
|
T62 |
1 |
| true |
417 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
116 |
1 |
|
T112 |
2 |
|
T305 |
1 |
|
T114 |
5 |
| others[1] |
88 |
1 |
|
T41 |
1 |
|
T112 |
2 |
|
T114 |
4 |
| others[2] |
110 |
1 |
|
T34 |
1 |
|
T112 |
4 |
|
T305 |
1 |
| others[3] |
156 |
1 |
|
T41 |
1 |
|
T127 |
1 |
|
T130 |
1 |
| false |
49 |
1 |
|
T112 |
3 |
|
T114 |
4 |
|
T81 |
2 |
| true |
13035 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T8 |
1 |
|
T25 |
1 |
|
T41 |
1 |
| others[1] |
235 |
1 |
|
T23 |
1 |
|
T127 |
1 |
|
T112 |
10 |
| others[2] |
228 |
1 |
|
T41 |
1 |
|
T110 |
1 |
|
T128 |
1 |
| others[3] |
398 |
1 |
|
T24 |
1 |
|
T34 |
1 |
|
T50 |
1 |
| false |
115 |
1 |
|
T16 |
1 |
|
T112 |
4 |
|
T114 |
5 |
| true |
12345 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
7695 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T60 |
2 |
| others[1] |
1090 |
1 |
|
T4 |
2 |
|
T5 |
1 |
|
T8 |
1 |
| others[2] |
1081 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
4 |
| others[3] |
1750 |
1 |
|
T4 |
3 |
|
T9 |
3 |
|
T33 |
1 |
| false |
555 |
1 |
|
T4 |
1 |
|
T9 |
1 |
|
T178 |
1 |
| true |
1383 |
1 |
|
T23 |
1 |
|
T13 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
249 |
1 |
|
T130 |
1 |
|
T112 |
8 |
|
T114 |
12 |
| others[1] |
217 |
1 |
|
T5 |
1 |
|
T111 |
1 |
|
T112 |
4 |
| others[2] |
231 |
1 |
|
T61 |
1 |
|
T112 |
11 |
|
T114 |
9 |
| others[3] |
414 |
1 |
|
T41 |
1 |
|
T51 |
1 |
|
T112 |
16 |
| false |
100 |
1 |
|
T112 |
11 |
|
T81 |
4 |
|
T381 |
1 |
| true |
12343 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
219 |
1 |
|
T118 |
1 |
|
T127 |
1 |
|
T128 |
1 |
| others[1] |
229 |
1 |
|
T112 |
8 |
|
T114 |
9 |
|
T308 |
1 |
| others[2] |
204 |
1 |
|
T41 |
1 |
|
T112 |
6 |
|
T305 |
1 |
| others[3] |
368 |
1 |
|
T5 |
1 |
|
T50 |
1 |
|
T112 |
16 |
| false |
116 |
1 |
|
T112 |
4 |
|
T114 |
4 |
|
T218 |
1 |
| true |
12418 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
7942 |
1 |
|
T4 |
1 |
|
T9 |
1 |
|
T17 |
1 |
| others[1] |
1228 |
1 |
|
T4 |
2 |
|
T16 |
1 |
|
T9 |
1 |
| others[2] |
1235 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T9 |
2 |
| others[3] |
2048 |
1 |
|
T4 |
4 |
|
T9 |
2 |
|
T45 |
1 |
| false |
666 |
1 |
|
T4 |
2 |
|
T9 |
1 |
|
T99 |
13 |
| true |
435 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1238 |
1 |
|
T16 |
1 |
|
T9 |
1 |
|
T23 |
1 |
| others[1] |
1242 |
1 |
|
T4 |
4 |
|
T9 |
1 |
|
T99 |
14 |
| others[2] |
1242 |
1 |
|
T4 |
2 |
|
T9 |
2 |
|
T99 |
16 |
| others[3] |
2079 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
5 |
| false |
645 |
1 |
|
T9 |
1 |
|
T99 |
16 |
|
T67 |
3 |
| true |
426 |
1 |
|
T5 |
1 |
|
T8 |
1 |
|
T33 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
102 |
1 |
|
T33 |
1 |
|
T110 |
1 |
|
T112 |
5 |
| others[1] |
111 |
1 |
|
T41 |
1 |
|
T112 |
3 |
|
T305 |
1 |
| others[2] |
102 |
1 |
|
T16 |
1 |
|
T41 |
1 |
|
T112 |
7 |
| others[3] |
162 |
1 |
|
T55 |
1 |
|
T112 |
9 |
|
T305 |
1 |
| false |
58 |
1 |
|
T112 |
2 |
|
T218 |
1 |
|
T81 |
1 |
| true |
6337 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
204 |
1 |
|
T33 |
1 |
|
T41 |
1 |
|
T127 |
1 |
| others[1] |
236 |
1 |
|
T5 |
1 |
|
T110 |
1 |
|
T112 |
13 |
| others[2] |
238 |
1 |
|
T16 |
1 |
|
T23 |
1 |
|
T25 |
1 |
| others[3] |
400 |
1 |
|
T50 |
1 |
|
T27 |
1 |
|
T130 |
1 |
| false |
110 |
1 |
|
T24 |
1 |
|
T118 |
1 |
|
T112 |
2 |
| true |
5684 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1102 |
1 |
|
T4 |
5 |
|
T5 |
1 |
|
T8 |
1 |
| others[1] |
1034 |
1 |
|
T4 |
1 |
|
T9 |
2 |
|
T45 |
1 |
| others[2] |
1059 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T9 |
1 |
| others[3] |
1761 |
1 |
|
T2 |
1 |
|
T4 |
2 |
|
T9 |
1 |
| false |
558 |
1 |
|
T4 |
2 |
|
T17 |
1 |
|
T23 |
1 |
| true |
1358 |
1 |
|
T33 |
1 |
|
T62 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
243 |
1 |
|
T5 |
1 |
|
T24 |
1 |
|
T128 |
1 |
| others[1] |
232 |
1 |
|
T127 |
1 |
|
T112 |
15 |
|
T114 |
8 |
| others[2] |
217 |
1 |
|
T8 |
1 |
|
T34 |
1 |
|
T112 |
10 |
| others[3] |
393 |
1 |
|
T33 |
1 |
|
T118 |
1 |
|
T112 |
11 |
| false |
120 |
1 |
|
T41 |
1 |
|
T112 |
7 |
|
T114 |
2 |
| true |
5667 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
235 |
1 |
|
T33 |
1 |
|
T112 |
16 |
|
T305 |
1 |
| others[1] |
221 |
1 |
|
T55 |
1 |
|
T112 |
11 |
|
T305 |
1 |
| others[2] |
225 |
1 |
|
T5 |
1 |
|
T112 |
7 |
|
T114 |
15 |
| others[3] |
371 |
1 |
|
T110 |
1 |
|
T130 |
1 |
|
T112 |
15 |
| false |
133 |
1 |
|
T112 |
3 |
|
T114 |
5 |
|
T309 |
1 |
| true |
5687 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1222 |
1 |
|
T2 |
1 |
|
T4 |
2 |
|
T17 |
1 |
| others[1] |
1212 |
1 |
|
T4 |
2 |
|
T16 |
1 |
|
T99 |
19 |
| others[2] |
1228 |
1 |
|
T4 |
2 |
|
T9 |
2 |
|
T182 |
1 |
| others[3] |
2126 |
1 |
|
T4 |
3 |
|
T9 |
4 |
|
T33 |
1 |
| false |
620 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T9 |
1 |
| true |
464 |
1 |
|
T5 |
1 |
|
T8 |
1 |
|
T23 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1227 |
1 |
|
T4 |
3 |
|
T9 |
3 |
|
T45 |
1 |
| others[1] |
1321 |
1 |
|
T4 |
1 |
|
T9 |
3 |
|
T99 |
24 |
| others[2] |
1240 |
1 |
|
T4 |
2 |
|
T24 |
1 |
|
T182 |
1 |
| others[3] |
2073 |
1 |
|
T4 |
3 |
|
T16 |
1 |
|
T9 |
1 |
| false |
588 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T99 |
11 |
| true |
423 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
81 |
1 |
|
T41 |
1 |
|
T112 |
6 |
|
T114 |
1 |
| others[1] |
107 |
1 |
|
T33 |
1 |
|
T112 |
7 |
|
T114 |
3 |
| others[2] |
114 |
1 |
|
T112 |
2 |
|
T305 |
1 |
|
T114 |
1 |
| others[3] |
153 |
1 |
|
T41 |
1 |
|
T112 |
3 |
|
T114 |
4 |
| false |
55 |
1 |
|
T112 |
1 |
|
T305 |
1 |
|
T114 |
3 |
| true |
6362 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
255 |
1 |
|
T33 |
1 |
|
T25 |
1 |
|
T27 |
1 |
| others[1] |
223 |
1 |
|
T8 |
1 |
|
T16 |
1 |
|
T50 |
1 |
| others[2] |
217 |
1 |
|
T5 |
1 |
|
T112 |
7 |
|
T114 |
10 |
| others[3] |
387 |
1 |
|
T34 |
1 |
|
T112 |
11 |
|
T31 |
1 |
| false |
135 |
1 |
|
T41 |
1 |
|
T127 |
1 |
|
T128 |
1 |
| true |
5655 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1029 |
1 |
|
T4 |
2 |
|
T9 |
1 |
|
T45 |
1 |
| others[1] |
1093 |
1 |
|
T2 |
1 |
|
T4 |
5 |
|
T9 |
2 |
| others[2] |
1038 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T9 |
2 |
| others[3] |
1753 |
1 |
|
T4 |
3 |
|
T8 |
1 |
|
T16 |
1 |
| false |
569 |
1 |
|
T54 |
1 |
|
T99 |
10 |
|
T34 |
1 |
| true |
1390 |
1 |
|
T5 |
1 |
|
T23 |
1 |
|
T62 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T33 |
1 |
|
T118 |
1 |
|
T25 |
1 |
| others[1] |
238 |
1 |
|
T41 |
1 |
|
T112 |
4 |
|
T114 |
10 |
| others[2] |
215 |
1 |
|
T5 |
1 |
|
T55 |
1 |
|
T51 |
1 |
| others[3] |
385 |
1 |
|
T8 |
1 |
|
T128 |
1 |
|
T112 |
21 |
| false |
109 |
1 |
|
T127 |
1 |
|
T112 |
4 |
|
T114 |
4 |
| true |
5699 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T16 |
1 |
|
T127 |
1 |
|
T112 |
7 |
| others[1] |
198 |
1 |
|
T33 |
1 |
|
T118 |
1 |
|
T41 |
1 |
| others[2] |
235 |
1 |
|
T55 |
1 |
|
T128 |
1 |
|
T112 |
15 |
| others[3] |
358 |
1 |
|
T112 |
13 |
|
T114 |
19 |
|
T215 |
1 |
| false |
129 |
1 |
|
T50 |
1 |
|
T112 |
5 |
|
T114 |
6 |
| true |
5728 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1265 |
1 |
|
T4 |
2 |
|
T45 |
1 |
|
T99 |
17 |
| others[1] |
1258 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T9 |
1 |
| others[2] |
1269 |
1 |
|
T4 |
2 |
|
T9 |
4 |
|
T23 |
1 |
| others[3] |
2030 |
1 |
|
T4 |
2 |
|
T16 |
1 |
|
T9 |
2 |
| false |
612 |
1 |
|
T4 |
3 |
|
T99 |
6 |
|
T109 |
7 |
| true |
438 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1182 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T9 |
2 |
| others[1] |
1290 |
1 |
|
T4 |
2 |
|
T9 |
1 |
|
T17 |
1 |
| others[2] |
1171 |
1 |
|
T9 |
1 |
|
T45 |
1 |
|
T99 |
18 |
| others[3] |
2110 |
1 |
|
T4 |
6 |
|
T16 |
1 |
|
T9 |
2 |
| false |
694 |
1 |
|
T4 |
1 |
|
T9 |
1 |
|
T99 |
6 |
| true |
425 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
86 |
1 |
|
T41 |
1 |
|
T112 |
5 |
|
T305 |
1 |
| others[1] |
105 |
1 |
|
T112 |
4 |
|
T114 |
1 |
|
T377 |
1 |
| others[2] |
113 |
1 |
|
T112 |
6 |
|
T114 |
3 |
|
T373 |
1 |
| others[3] |
202 |
1 |
|
T41 |
1 |
|
T112 |
8 |
|
T305 |
1 |
| false |
55 |
1 |
|
T112 |
4 |
|
T114 |
2 |
|
T308 |
1 |
| true |
6311 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
242 |
1 |
|
T8 |
1 |
|
T118 |
1 |
|
T41 |
1 |
| others[1] |
228 |
1 |
|
T112 |
9 |
|
T114 |
14 |
|
T377 |
1 |
| others[2] |
224 |
1 |
|
T5 |
1 |
|
T23 |
1 |
|
T24 |
1 |
| others[3] |
371 |
1 |
|
T16 |
1 |
|
T112 |
18 |
|
T114 |
18 |
| false |
123 |
1 |
|
T112 |
5 |
|
T114 |
7 |
|
T81 |
3 |
| true |
5684 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1079 |
1 |
|
T4 |
3 |
|
T7 |
1 |
|
T177 |
1 |
| others[1] |
1028 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
| others[2] |
1029 |
1 |
|
T4 |
1 |
|
T9 |
3 |
|
T17 |
1 |
| others[3] |
1806 |
1 |
|
T4 |
6 |
|
T5 |
1 |
|
T16 |
1 |
| false |
517 |
1 |
|
T99 |
5 |
|
T67 |
3 |
|
T109 |
7 |
| true |
1413 |
1 |
|
T33 |
1 |
|
T13 |
1 |
|
T54 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
223 |
1 |
|
T25 |
1 |
|
T50 |
1 |
|
T112 |
18 |
| others[1] |
243 |
1 |
|
T112 |
10 |
|
T114 |
5 |
|
T227 |
1 |
| others[2] |
220 |
1 |
|
T5 |
1 |
|
T8 |
1 |
|
T118 |
1 |
| others[3] |
365 |
1 |
|
T24 |
1 |
|
T130 |
1 |
|
T112 |
20 |
| false |
135 |
1 |
|
T110 |
1 |
|
T112 |
6 |
|
T31 |
1 |
| true |
5686 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T5 |
1 |
|
T61 |
1 |
|
T110 |
1 |
| others[1] |
212 |
1 |
|
T34 |
1 |
|
T130 |
1 |
|
T112 |
10 |
| others[2] |
217 |
1 |
|
T16 |
1 |
|
T51 |
1 |
|
T127 |
1 |
| others[3] |
334 |
1 |
|
T41 |
1 |
|
T112 |
19 |
|
T305 |
1 |
| false |
128 |
1 |
|
T55 |
1 |
|
T112 |
4 |
|
T114 |
4 |
| true |
5752 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1236 |
1 |
|
T4 |
1 |
|
T9 |
2 |
|
T45 |
1 |
| others[1] |
1218 |
1 |
|
T4 |
2 |
|
T5 |
1 |
|
T99 |
23 |
| others[2] |
1271 |
1 |
|
T4 |
3 |
|
T16 |
1 |
|
T9 |
1 |
| others[3] |
2057 |
1 |
|
T3 |
1 |
|
T4 |
4 |
|
T9 |
3 |
| false |
657 |
1 |
|
T4 |
1 |
|
T9 |
1 |
|
T182 |
1 |
| true |
433 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T33 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1239 |
1 |
|
T3 |
1 |
|
T4 |
5 |
|
T16 |
1 |
| others[1] |
1271 |
1 |
|
T4 |
3 |
|
T99 |
21 |
|
T57 |
1 |
| others[2] |
1227 |
1 |
|
T4 |
1 |
|
T55 |
1 |
|
T99 |
15 |
| others[3] |
2074 |
1 |
|
T4 |
2 |
|
T9 |
2 |
|
T17 |
1 |
| false |
635 |
1 |
|
T9 |
3 |
|
T99 |
11 |
|
T67 |
3 |
| true |
426 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |