Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
89 |
1 |
|
T41 |
1 |
|
T112 |
4 |
|
T114 |
3 |
| others[1] |
111 |
1 |
|
T112 |
3 |
|
T305 |
1 |
|
T114 |
4 |
| others[2] |
119 |
1 |
|
T16 |
1 |
|
T41 |
1 |
|
T130 |
1 |
| others[3] |
165 |
1 |
|
T55 |
1 |
|
T112 |
4 |
|
T305 |
1 |
| false |
69 |
1 |
|
T112 |
4 |
|
T114 |
1 |
|
T377 |
1 |
| true |
6319 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T118 |
1 |
|
T50 |
1 |
|
T110 |
1 |
| others[1] |
225 |
1 |
|
T27 |
1 |
|
T127 |
1 |
|
T112 |
11 |
| others[2] |
227 |
1 |
|
T41 |
1 |
|
T26 |
1 |
|
T112 |
11 |
| others[3] |
400 |
1 |
|
T8 |
1 |
|
T41 |
1 |
|
T34 |
1 |
| false |
118 |
1 |
|
T112 |
4 |
|
T114 |
4 |
|
T215 |
1 |
| true |
5663 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1074 |
1 |
|
T4 |
4 |
|
T9 |
1 |
|
T13 |
1 |
| others[1] |
1025 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T9 |
1 |
| others[2] |
1078 |
1 |
|
T9 |
2 |
|
T17 |
1 |
|
T62 |
1 |
| others[3] |
1770 |
1 |
|
T4 |
3 |
|
T16 |
1 |
|
T7 |
1 |
| false |
595 |
1 |
|
T4 |
1 |
|
T9 |
3 |
|
T99 |
4 |
| true |
1330 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
243 |
1 |
|
T34 |
1 |
|
T127 |
1 |
|
T112 |
10 |
| others[1] |
227 |
1 |
|
T16 |
1 |
|
T27 |
1 |
|
T112 |
8 |
| others[2] |
224 |
1 |
|
T25 |
1 |
|
T41 |
1 |
|
T112 |
12 |
| others[3] |
384 |
1 |
|
T51 |
1 |
|
T128 |
1 |
|
T112 |
17 |
| false |
103 |
1 |
|
T55 |
1 |
|
T112 |
6 |
|
T114 |
5 |
| true |
5691 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
207 |
1 |
|
T112 |
10 |
|
T114 |
10 |
|
T377 |
1 |
| others[1] |
220 |
1 |
|
T16 |
1 |
|
T130 |
1 |
|
T112 |
14 |
| others[2] |
224 |
1 |
|
T50 |
1 |
|
T110 |
1 |
|
T112 |
9 |
| others[3] |
352 |
1 |
|
T41 |
1 |
|
T112 |
19 |
|
T305 |
2 |
| false |
109 |
1 |
|
T34 |
1 |
|
T127 |
1 |
|
T112 |
4 |
| true |
5760 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1196 |
1 |
|
T3 |
1 |
|
T9 |
3 |
|
T17 |
1 |
| others[1] |
1195 |
1 |
|
T4 |
2 |
|
T16 |
1 |
|
T45 |
1 |
| others[2] |
1270 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T99 |
18 |
| others[3] |
2104 |
1 |
|
T2 |
1 |
|
T4 |
7 |
|
T9 |
4 |
| false |
663 |
1 |
|
T4 |
1 |
|
T99 |
10 |
|
T67 |
1 |
| true |
444 |
1 |
|
T5 |
1 |
|
T8 |
1 |
|
T33 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1256 |
1 |
|
T4 |
2 |
|
T16 |
1 |
|
T17 |
1 |
| others[1] |
1184 |
1 |
|
T4 |
1 |
|
T9 |
3 |
|
T55 |
1 |
| others[2] |
1236 |
1 |
|
T4 |
1 |
|
T9 |
1 |
|
T45 |
1 |
| others[3] |
2119 |
1 |
|
T4 |
4 |
|
T9 |
3 |
|
T182 |
1 |
| false |
651 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T99 |
12 |
| true |
426 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
103 |
1 |
|
T112 |
2 |
|
T305 |
1 |
|
T114 |
5 |
| others[1] |
111 |
1 |
|
T41 |
1 |
|
T130 |
1 |
|
T112 |
2 |
| others[2] |
108 |
1 |
|
T41 |
1 |
|
T112 |
5 |
|
T114 |
6 |
| others[3] |
165 |
1 |
|
T112 |
10 |
|
T114 |
3 |
|
T308 |
2 |
| false |
62 |
1 |
|
T112 |
2 |
|
T305 |
1 |
|
T114 |
1 |
| true |
6323 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
259 |
1 |
|
T8 |
1 |
|
T118 |
1 |
|
T25 |
1 |
| others[1] |
228 |
1 |
|
T16 |
1 |
|
T33 |
1 |
|
T130 |
1 |
| others[2] |
215 |
1 |
|
T41 |
1 |
|
T112 |
15 |
|
T114 |
10 |
| others[3] |
402 |
1 |
|
T55 |
1 |
|
T61 |
1 |
|
T112 |
23 |
| false |
120 |
1 |
|
T24 |
1 |
|
T50 |
1 |
|
T112 |
3 |
| true |
5648 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1051 |
1 |
|
T2 |
1 |
|
T4 |
2 |
|
T9 |
1 |
| others[1] |
1062 |
1 |
|
T9 |
1 |
|
T45 |
1 |
|
T18 |
1 |
| others[2] |
1085 |
1 |
|
T4 |
4 |
|
T8 |
1 |
|
T9 |
2 |
| others[3] |
1731 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T16 |
1 |
| false |
553 |
1 |
|
T4 |
2 |
|
T9 |
1 |
|
T7 |
1 |
| true |
1390 |
1 |
|
T5 |
1 |
|
T23 |
1 |
|
T62 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T24 |
1 |
|
T34 |
1 |
|
T50 |
1 |
| others[1] |
228 |
1 |
|
T118 |
1 |
|
T51 |
1 |
|
T112 |
8 |
| others[2] |
230 |
1 |
|
T112 |
7 |
|
T114 |
10 |
|
T227 |
1 |
| others[3] |
409 |
1 |
|
T25 |
1 |
|
T41 |
1 |
|
T112 |
13 |
| false |
115 |
1 |
|
T112 |
3 |
|
T114 |
5 |
|
T81 |
6 |
| true |
5658 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
198 |
1 |
|
T16 |
1 |
|
T127 |
1 |
|
T130 |
1 |
| others[1] |
210 |
1 |
|
T5 |
1 |
|
T41 |
1 |
|
T51 |
1 |
| others[2] |
218 |
1 |
|
T55 |
1 |
|
T41 |
1 |
|
T112 |
13 |
| others[3] |
383 |
1 |
|
T34 |
1 |
|
T50 |
1 |
|
T61 |
1 |
| false |
100 |
1 |
|
T128 |
1 |
|
T112 |
6 |
|
T114 |
1 |
| true |
5763 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1262 |
1 |
|
T4 |
5 |
|
T17 |
1 |
|
T33 |
1 |
| others[1] |
1249 |
1 |
|
T4 |
1 |
|
T9 |
2 |
|
T54 |
1 |
| others[2] |
1293 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T9 |
1 |
| others[3] |
2029 |
1 |
|
T2 |
1 |
|
T4 |
4 |
|
T9 |
4 |
| false |
603 |
1 |
|
T4 |
1 |
|
T99 |
11 |
|
T21 |
1 |
| true |
436 |
1 |
|
T5 |
1 |
|
T8 |
1 |
|
T23 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1177 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T16 |
1 |
| others[1] |
1194 |
1 |
|
T4 |
3 |
|
T9 |
2 |
|
T24 |
1 |
| others[2] |
1351 |
1 |
|
T4 |
3 |
|
T17 |
1 |
|
T7 |
1 |
| others[3] |
2031 |
1 |
|
T4 |
3 |
|
T9 |
3 |
|
T23 |
1 |
| false |
702 |
1 |
|
T9 |
1 |
|
T45 |
1 |
|
T99 |
4 |
| true |
417 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
99 |
1 |
|
T33 |
1 |
|
T112 |
5 |
|
T114 |
4 |
| others[1] |
98 |
1 |
|
T41 |
1 |
|
T34 |
1 |
|
T127 |
1 |
| others[2] |
107 |
1 |
|
T130 |
1 |
|
T112 |
5 |
|
T114 |
2 |
| others[3] |
204 |
1 |
|
T41 |
1 |
|
T128 |
1 |
|
T112 |
7 |
| false |
55 |
1 |
|
T112 |
1 |
|
T377 |
1 |
|
T81 |
2 |
| true |
6309 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
266 |
1 |
|
T27 |
1 |
|
T111 |
1 |
|
T112 |
14 |
| others[1] |
202 |
1 |
|
T33 |
1 |
|
T41 |
1 |
|
T128 |
1 |
| others[2] |
253 |
1 |
|
T24 |
1 |
|
T112 |
10 |
|
T114 |
8 |
| others[3] |
385 |
1 |
|
T5 |
1 |
|
T23 |
1 |
|
T41 |
1 |
| false |
120 |
1 |
|
T112 |
5 |
|
T305 |
1 |
|
T114 |
4 |
| true |
5646 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1090 |
1 |
|
T4 |
1 |
|
T9 |
1 |
|
T182 |
1 |
| others[1] |
1031 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T16 |
1 |
| others[2] |
992 |
1 |
|
T4 |
2 |
|
T99 |
10 |
|
T38 |
1 |
| others[3] |
1817 |
1 |
|
T4 |
5 |
|
T8 |
1 |
|
T9 |
1 |
| false |
541 |
1 |
|
T4 |
2 |
|
T9 |
1 |
|
T7 |
1 |
| true |
1401 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T33 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T41 |
1 |
|
T50 |
1 |
|
T112 |
9 |
| others[1] |
267 |
1 |
|
T130 |
1 |
|
T112 |
9 |
|
T114 |
12 |
| others[2] |
203 |
1 |
|
T33 |
1 |
|
T112 |
10 |
|
T114 |
8 |
| others[3] |
404 |
1 |
|
T25 |
1 |
|
T127 |
1 |
|
T112 |
22 |
| false |
122 |
1 |
|
T5 |
1 |
|
T112 |
3 |
|
T114 |
7 |
| true |
5652 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
190 |
1 |
|
T112 |
9 |
|
T114 |
7 |
|
T377 |
1 |
| others[1] |
208 |
1 |
|
T50 |
1 |
|
T112 |
10 |
|
T114 |
10 |
| others[2] |
224 |
1 |
|
T5 |
1 |
|
T128 |
1 |
|
T112 |
13 |
| others[3] |
403 |
1 |
|
T61 |
1 |
|
T110 |
1 |
|
T112 |
18 |
| false |
118 |
1 |
|
T130 |
1 |
|
T112 |
6 |
|
T114 |
6 |
| true |
5729 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1301 |
1 |
|
T2 |
1 |
|
T4 |
2 |
|
T62 |
1 |
| others[1] |
1267 |
1 |
|
T4 |
3 |
|
T16 |
1 |
|
T9 |
2 |
| others[2] |
1232 |
1 |
|
T4 |
1 |
|
T182 |
1 |
|
T118 |
1 |
| others[3] |
2026 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T9 |
4 |
| false |
606 |
1 |
|
T4 |
3 |
|
T9 |
1 |
|
T99 |
6 |
| true |
440 |
1 |
|
T5 |
1 |
|
T8 |
1 |
|
T33 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1209 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T7 |
1 |
| others[1] |
1179 |
1 |
|
T9 |
1 |
|
T99 |
16 |
|
T38 |
1 |
| others[2] |
1327 |
1 |
|
T4 |
3 |
|
T9 |
2 |
|
T99 |
19 |
| others[3] |
2066 |
1 |
|
T4 |
6 |
|
T16 |
1 |
|
T9 |
3 |
| false |
657 |
1 |
|
T9 |
1 |
|
T182 |
1 |
|
T99 |
8 |
| true |
434 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
105 |
1 |
|
T112 |
6 |
|
T114 |
7 |
|
T81 |
6 |
| others[1] |
115 |
1 |
|
T55 |
1 |
|
T112 |
5 |
|
T305 |
1 |
| others[2] |
96 |
1 |
|
T33 |
1 |
|
T112 |
6 |
|
T114 |
3 |
| others[3] |
169 |
1 |
|
T41 |
2 |
|
T112 |
7 |
|
T305 |
1 |
| false |
62 |
1 |
|
T112 |
1 |
|
T114 |
4 |
|
T308 |
1 |
| true |
6325 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T55 |
1 |
|
T27 |
1 |
|
T26 |
1 |
| others[1] |
235 |
1 |
|
T34 |
1 |
|
T112 |
9 |
|
T114 |
9 |
| others[2] |
246 |
1 |
|
T25 |
1 |
|
T41 |
1 |
|
T110 |
1 |
| others[3] |
385 |
1 |
|
T5 |
1 |
|
T33 |
1 |
|
T128 |
1 |
| false |
115 |
1 |
|
T24 |
1 |
|
T118 |
1 |
|
T61 |
1 |
| true |
5667 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1065 |
1 |
|
T4 |
2 |
|
T5 |
1 |
|
T8 |
1 |
| others[1] |
1067 |
1 |
|
T4 |
2 |
|
T9 |
3 |
|
T17 |
1 |
| others[2] |
1048 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
2 |
| others[3] |
1776 |
1 |
|
T4 |
5 |
|
T16 |
1 |
|
T9 |
2 |
| false |
532 |
1 |
|
T99 |
4 |
|
T21 |
1 |
|
T71 |
1 |
| true |
1384 |
1 |
|
T62 |
1 |
|
T178 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T130 |
1 |
|
T112 |
9 |
|
T114 |
7 |
| others[1] |
241 |
1 |
|
T5 |
1 |
|
T50 |
1 |
|
T128 |
1 |
| others[2] |
227 |
1 |
|
T34 |
1 |
|
T51 |
1 |
|
T127 |
1 |
| others[3] |
360 |
1 |
|
T16 |
1 |
|
T24 |
1 |
|
T55 |
1 |
| false |
120 |
1 |
|
T112 |
6 |
|
T114 |
6 |
|
T102 |
1 |
| true |
5700 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T112 |
9 |
|
T114 |
13 |
|
T103 |
1 |
| others[1] |
208 |
1 |
|
T34 |
1 |
|
T112 |
12 |
|
T114 |
11 |
| others[2] |
216 |
1 |
|
T41 |
1 |
|
T112 |
9 |
|
T114 |
9 |
| others[3] |
378 |
1 |
|
T16 |
1 |
|
T112 |
18 |
|
T114 |
16 |
| false |
109 |
1 |
|
T110 |
1 |
|
T130 |
1 |
|
T112 |
3 |
| true |
5732 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1227 |
1 |
|
T4 |
3 |
|
T9 |
1 |
|
T17 |
1 |
| others[1] |
1219 |
1 |
|
T4 |
1 |
|
T9 |
2 |
|
T45 |
1 |
| others[2] |
1247 |
1 |
|
T4 |
2 |
|
T5 |
1 |
|
T9 |
2 |
| others[3] |
2089 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T9 |
2 |
| false |
649 |
1 |
|
T4 |
3 |
|
T16 |
1 |
|
T55 |
1 |
| true |
441 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T33 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1267 |
1 |
|
T4 |
4 |
|
T9 |
1 |
|
T99 |
22 |
| others[1] |
1263 |
1 |
|
T4 |
2 |
|
T16 |
1 |
|
T9 |
1 |
| others[2] |
1207 |
1 |
|
T2 |
1 |
|
T4 |
3 |
|
T9 |
2 |
| others[3] |
2067 |
1 |
|
T4 |
1 |
|
T9 |
3 |
|
T23 |
1 |
| false |
640 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T99 |
5 |
| true |
428 |
1 |
|
T5 |
1 |
|
T8 |
1 |
|
T33 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
95 |
1 |
|
T130 |
1 |
|
T112 |
4 |
|
T114 |
1 |
| others[1] |
103 |
1 |
|
T41 |
1 |
|
T112 |
2 |
|
T114 |
5 |
| others[2] |
114 |
1 |
|
T110 |
1 |
|
T112 |
3 |
|
T305 |
1 |
| others[3] |
162 |
1 |
|
T16 |
1 |
|
T41 |
1 |
|
T112 |
5 |
| false |
61 |
1 |
|
T112 |
1 |
|
T305 |
1 |
|
T114 |
5 |
| true |
6337 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
200 |
1 |
|
T33 |
1 |
|
T50 |
1 |
|
T27 |
1 |
| others[1] |
251 |
1 |
|
T8 |
1 |
|
T118 |
1 |
|
T111 |
1 |
| others[2] |
254 |
1 |
|
T127 |
1 |
|
T128 |
1 |
|
T26 |
1 |
| others[3] |
417 |
1 |
|
T5 |
1 |
|
T25 |
1 |
|
T34 |
1 |
| false |
125 |
1 |
|
T23 |
1 |
|
T51 |
1 |
|
T112 |
8 |
| true |
5625 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1073 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T9 |
2 |
| others[1] |
1046 |
1 |
|
T2 |
1 |
|
T4 |
3 |
|
T16 |
1 |
| others[2] |
1047 |
1 |
|
T4 |
2 |
|
T9 |
3 |
|
T7 |
1 |
| others[3] |
1741 |
1 |
|
T4 |
1 |
|
T9 |
1 |
|
T17 |
1 |
| false |
568 |
1 |
|
T4 |
2 |
|
T9 |
1 |
|
T45 |
1 |
| true |
1397 |
1 |
|
T5 |
1 |
|
T8 |
1 |
|
T33 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |