Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T16 |
1 |
|
T41 |
1 |
|
T112 |
7 |
| others[1] |
226 |
1 |
|
T8 |
1 |
|
T50 |
1 |
|
T112 |
7 |
| others[2] |
228 |
1 |
|
T41 |
1 |
|
T51 |
1 |
|
T130 |
1 |
| others[3] |
358 |
1 |
|
T55 |
1 |
|
T110 |
1 |
|
T27 |
1 |
| false |
123 |
1 |
|
T112 |
9 |
|
T114 |
2 |
|
T81 |
7 |
| true |
5719 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
219 |
1 |
|
T55 |
1 |
|
T112 |
6 |
|
T114 |
11 |
| others[1] |
226 |
1 |
|
T5 |
1 |
|
T118 |
1 |
|
T34 |
1 |
| others[2] |
218 |
1 |
|
T51 |
1 |
|
T61 |
1 |
|
T112 |
9 |
| others[3] |
348 |
1 |
|
T112 |
20 |
|
T114 |
12 |
|
T377 |
1 |
| false |
139 |
1 |
|
T128 |
1 |
|
T112 |
3 |
|
T114 |
5 |
| true |
5722 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1253 |
1 |
|
T4 |
2 |
|
T16 |
1 |
|
T9 |
2 |
| others[1] |
1284 |
1 |
|
T4 |
6 |
|
T9 |
1 |
|
T62 |
1 |
| others[2] |
1240 |
1 |
|
T9 |
2 |
|
T182 |
1 |
|
T99 |
13 |
| others[3] |
2020 |
1 |
|
T4 |
2 |
|
T9 |
2 |
|
T17 |
1 |
| false |
636 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T55 |
1 |
| true |
439 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1247 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T16 |
1 |
| others[1] |
1203 |
1 |
|
T4 |
1 |
|
T9 |
2 |
|
T45 |
1 |
| others[2] |
1263 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T9 |
1 |
| others[3] |
2109 |
1 |
|
T4 |
5 |
|
T9 |
3 |
|
T17 |
1 |
| false |
635 |
1 |
|
T4 |
2 |
|
T23 |
1 |
|
T182 |
1 |
| true |
415 |
1 |
|
T5 |
1 |
|
T8 |
1 |
|
T33 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
123 |
1 |
|
T55 |
1 |
|
T110 |
1 |
|
T112 |
2 |
| others[1] |
109 |
1 |
|
T41 |
1 |
|
T61 |
1 |
|
T128 |
1 |
| others[2] |
113 |
1 |
|
T16 |
1 |
|
T112 |
7 |
|
T114 |
6 |
| others[3] |
166 |
1 |
|
T41 |
1 |
|
T130 |
1 |
|
T112 |
6 |
| false |
62 |
1 |
|
T33 |
1 |
|
T112 |
2 |
|
T114 |
4 |
| true |
6299 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
258 |
1 |
|
T23 |
1 |
|
T118 |
1 |
|
T41 |
2 |
| others[1] |
245 |
1 |
|
T112 |
9 |
|
T114 |
10 |
|
T215 |
1 |
| others[2] |
228 |
1 |
|
T25 |
1 |
|
T51 |
1 |
|
T27 |
1 |
| others[3] |
404 |
1 |
|
T16 |
1 |
|
T34 |
1 |
|
T127 |
1 |
| false |
108 |
1 |
|
T112 |
4 |
|
T114 |
6 |
|
T227 |
1 |
| true |
5629 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1001 |
1 |
|
T4 |
2 |
|
T9 |
3 |
|
T24 |
1 |
| others[1] |
1111 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
| others[2] |
1125 |
1 |
|
T4 |
3 |
|
T5 |
1 |
|
T17 |
1 |
| others[3] |
1767 |
1 |
|
T4 |
3 |
|
T8 |
1 |
|
T16 |
1 |
| false |
526 |
1 |
|
T25 |
1 |
|
T99 |
5 |
|
T100 |
1 |
| true |
1342 |
1 |
|
T13 |
1 |
|
T54 |
1 |
|
T178 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
238 |
1 |
|
T33 |
1 |
|
T111 |
1 |
|
T112 |
11 |
| others[1] |
224 |
1 |
|
T24 |
1 |
|
T112 |
8 |
|
T305 |
1 |
| others[2] |
214 |
1 |
|
T112 |
13 |
|
T114 |
11 |
|
T215 |
1 |
| others[3] |
383 |
1 |
|
T16 |
1 |
|
T41 |
1 |
|
T51 |
1 |
| false |
137 |
1 |
|
T41 |
1 |
|
T110 |
1 |
|
T112 |
5 |
| true |
5676 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
206 |
1 |
|
T50 |
1 |
|
T112 |
12 |
|
T114 |
10 |
| others[1] |
183 |
1 |
|
T16 |
1 |
|
T112 |
4 |
|
T114 |
8 |
| others[2] |
249 |
1 |
|
T33 |
1 |
|
T41 |
1 |
|
T112 |
13 |
| others[3] |
367 |
1 |
|
T55 |
1 |
|
T34 |
1 |
|
T61 |
1 |
| false |
112 |
1 |
|
T130 |
1 |
|
T112 |
3 |
|
T114 |
4 |
| true |
5755 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1234 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T9 |
1 |
| others[1] |
1233 |
1 |
|
T4 |
1 |
|
T9 |
1 |
|
T62 |
1 |
| others[2] |
1238 |
1 |
|
T4 |
4 |
|
T16 |
1 |
|
T9 |
2 |
| others[3] |
2122 |
1 |
|
T4 |
4 |
|
T9 |
1 |
|
T99 |
40 |
| false |
617 |
1 |
|
T9 |
2 |
|
T99 |
9 |
|
T67 |
1 |
| true |
428 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1281 |
1 |
|
T4 |
3 |
|
T16 |
1 |
|
T9 |
3 |
| others[1] |
1180 |
1 |
|
T2 |
1 |
|
T4 |
2 |
|
T9 |
1 |
| others[2] |
1256 |
1 |
|
T3 |
1 |
|
T9 |
1 |
|
T62 |
1 |
| others[3] |
2084 |
1 |
|
T4 |
3 |
|
T9 |
2 |
|
T45 |
1 |
| false |
646 |
1 |
|
T4 |
3 |
|
T55 |
1 |
|
T99 |
7 |
| true |
425 |
1 |
|
T5 |
1 |
|
T8 |
1 |
|
T33 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
120 |
1 |
|
T41 |
1 |
|
T112 |
3 |
|
T305 |
1 |
| others[1] |
113 |
1 |
|
T55 |
1 |
|
T41 |
1 |
|
T112 |
2 |
| others[2] |
105 |
1 |
|
T34 |
1 |
|
T51 |
1 |
|
T112 |
5 |
| others[3] |
154 |
1 |
|
T112 |
8 |
|
T114 |
5 |
|
T81 |
7 |
| false |
53 |
1 |
|
T112 |
1 |
|
T114 |
1 |
|
T373 |
1 |
| true |
6327 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T5 |
1 |
|
T8 |
1 |
|
T55 |
1 |
| others[1] |
230 |
1 |
|
T33 |
1 |
|
T112 |
14 |
|
T114 |
8 |
| others[2] |
255 |
1 |
|
T112 |
14 |
|
T31 |
1 |
|
T114 |
15 |
| others[3] |
366 |
1 |
|
T41 |
1 |
|
T127 |
1 |
|
T130 |
1 |
| false |
112 |
1 |
|
T24 |
1 |
|
T118 |
1 |
|
T41 |
1 |
| true |
5693 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1098 |
1 |
|
T4 |
3 |
|
T16 |
1 |
|
T9 |
2 |
| others[1] |
1025 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T9 |
1 |
| others[2] |
1103 |
1 |
|
T2 |
1 |
|
T4 |
3 |
|
T5 |
1 |
| others[3] |
1700 |
1 |
|
T4 |
1 |
|
T9 |
3 |
|
T17 |
1 |
| false |
554 |
1 |
|
T4 |
2 |
|
T99 |
7 |
|
T67 |
1 |
| true |
1392 |
1 |
|
T8 |
1 |
|
T23 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
273 |
1 |
|
T55 |
1 |
|
T128 |
1 |
|
T112 |
14 |
| others[1] |
213 |
1 |
|
T41 |
1 |
|
T112 |
7 |
|
T114 |
11 |
| others[2] |
226 |
1 |
|
T16 |
1 |
|
T24 |
1 |
|
T112 |
10 |
| others[3] |
381 |
1 |
|
T5 |
1 |
|
T8 |
1 |
|
T118 |
1 |
| false |
127 |
1 |
|
T51 |
1 |
|
T112 |
3 |
|
T114 |
4 |
| true |
5652 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
213 |
1 |
|
T5 |
1 |
|
T34 |
1 |
|
T50 |
1 |
| others[1] |
241 |
1 |
|
T112 |
11 |
|
T114 |
9 |
|
T215 |
1 |
| others[2] |
213 |
1 |
|
T112 |
9 |
|
T114 |
10 |
|
T218 |
1 |
| others[3] |
361 |
1 |
|
T16 |
1 |
|
T55 |
1 |
|
T112 |
13 |
| false |
115 |
1 |
|
T41 |
1 |
|
T127 |
1 |
|
T112 |
6 |
| true |
5729 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1267 |
1 |
|
T2 |
1 |
|
T4 |
2 |
|
T9 |
1 |
| others[1] |
1236 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T9 |
1 |
| others[2] |
1255 |
1 |
|
T4 |
3 |
|
T9 |
1 |
|
T7 |
1 |
| others[3] |
2035 |
1 |
|
T4 |
5 |
|
T9 |
2 |
|
T17 |
1 |
| false |
629 |
1 |
|
T4 |
1 |
|
T9 |
2 |
|
T182 |
1 |
| true |
450 |
1 |
|
T5 |
1 |
|
T8 |
1 |
|
T33 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1281 |
1 |
|
T3 |
1 |
|
T9 |
2 |
|
T55 |
1 |
| others[1] |
1290 |
1 |
|
T4 |
3 |
|
T9 |
1 |
|
T99 |
20 |
| others[2] |
1228 |
1 |
|
T4 |
3 |
|
T45 |
1 |
|
T7 |
1 |
| others[3] |
2028 |
1 |
|
T4 |
5 |
|
T16 |
1 |
|
T9 |
3 |
| false |
612 |
1 |
|
T9 |
1 |
|
T99 |
11 |
|
T67 |
3 |
| true |
433 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
110 |
1 |
|
T112 |
3 |
|
T114 |
6 |
|
T377 |
1 |
| others[1] |
112 |
1 |
|
T33 |
1 |
|
T112 |
8 |
|
T114 |
3 |
| others[2] |
106 |
1 |
|
T55 |
1 |
|
T41 |
1 |
|
T112 |
4 |
| others[3] |
167 |
1 |
|
T16 |
1 |
|
T41 |
1 |
|
T127 |
1 |
| false |
51 |
1 |
|
T112 |
2 |
|
T81 |
3 |
|
T382 |
1 |
| true |
6326 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
204 |
1 |
|
T8 |
1 |
|
T112 |
7 |
|
T114 |
8 |
| others[1] |
261 |
1 |
|
T33 |
1 |
|
T127 |
1 |
|
T26 |
1 |
| others[2] |
196 |
1 |
|
T41 |
1 |
|
T112 |
7 |
|
T305 |
1 |
| others[3] |
392 |
1 |
|
T61 |
1 |
|
T27 |
1 |
|
T128 |
1 |
| false |
114 |
1 |
|
T24 |
1 |
|
T112 |
4 |
|
T114 |
6 |
| true |
5705 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1046 |
1 |
|
T4 |
1 |
|
T9 |
1 |
|
T54 |
1 |
| others[1] |
1056 |
1 |
|
T2 |
1 |
|
T4 |
4 |
|
T17 |
1 |
| others[2] |
1042 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T9 |
3 |
| others[3] |
1767 |
1 |
|
T4 |
5 |
|
T8 |
1 |
|
T9 |
3 |
| false |
554 |
1 |
|
T3 |
1 |
|
T177 |
1 |
|
T99 |
9 |
| true |
1407 |
1 |
|
T5 |
1 |
|
T62 |
1 |
|
T178 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T25 |
1 |
|
T112 |
9 |
|
T114 |
8 |
| others[1] |
243 |
1 |
|
T16 |
1 |
|
T33 |
1 |
|
T112 |
7 |
| others[2] |
250 |
1 |
|
T51 |
1 |
|
T61 |
1 |
|
T112 |
11 |
| others[3] |
364 |
1 |
|
T8 |
1 |
|
T50 |
1 |
|
T112 |
21 |
| false |
122 |
1 |
|
T27 |
1 |
|
T112 |
7 |
|
T114 |
4 |
| true |
5661 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
214 |
1 |
|
T16 |
1 |
|
T118 |
1 |
|
T127 |
1 |
| others[1] |
232 |
1 |
|
T41 |
1 |
|
T128 |
1 |
|
T112 |
14 |
| others[2] |
204 |
1 |
|
T33 |
1 |
|
T34 |
1 |
|
T112 |
10 |
| others[3] |
363 |
1 |
|
T130 |
1 |
|
T112 |
18 |
|
T305 |
1 |
| false |
107 |
1 |
|
T112 |
4 |
|
T114 |
7 |
|
T377 |
1 |
| true |
5752 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1274 |
1 |
|
T4 |
2 |
|
T16 |
1 |
|
T99 |
10 |
| others[1] |
1264 |
1 |
|
T4 |
5 |
|
T9 |
2 |
|
T99 |
24 |
| others[2] |
1275 |
1 |
|
T9 |
3 |
|
T178 |
1 |
|
T118 |
1 |
| others[3] |
2039 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T9 |
2 |
| false |
580 |
1 |
|
T4 |
1 |
|
T62 |
1 |
|
T99 |
12 |
| true |
440 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1233 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T16 |
1 |
| others[1] |
1214 |
1 |
|
T4 |
2 |
|
T9 |
4 |
|
T99 |
16 |
| others[2] |
1210 |
1 |
|
T4 |
1 |
|
T9 |
1 |
|
T99 |
18 |
| others[3] |
2086 |
1 |
|
T4 |
3 |
|
T9 |
1 |
|
T45 |
1 |
| false |
702 |
1 |
|
T4 |
3 |
|
T17 |
1 |
|
T7 |
1 |
| true |
427 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
82 |
1 |
|
T41 |
2 |
|
T51 |
1 |
|
T112 |
4 |
| others[1] |
121 |
1 |
|
T128 |
1 |
|
T112 |
6 |
|
T305 |
1 |
| others[2] |
101 |
1 |
|
T130 |
1 |
|
T112 |
1 |
|
T114 |
6 |
| others[3] |
180 |
1 |
|
T16 |
1 |
|
T112 |
11 |
|
T114 |
4 |
| false |
65 |
1 |
|
T112 |
4 |
|
T305 |
1 |
|
T114 |
2 |
| true |
6323 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
230 |
1 |
|
T8 |
1 |
|
T16 |
1 |
|
T112 |
9 |
| others[1] |
243 |
1 |
|
T112 |
9 |
|
T114 |
9 |
|
T377 |
1 |
| others[2] |
242 |
1 |
|
T25 |
1 |
|
T111 |
1 |
|
T112 |
9 |
| others[3] |
374 |
1 |
|
T51 |
1 |
|
T61 |
1 |
|
T26 |
1 |
| false |
115 |
1 |
|
T127 |
1 |
|
T112 |
7 |
|
T114 |
12 |
| true |
5668 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1085 |
1 |
|
T4 |
3 |
|
T9 |
2 |
|
T99 |
13 |
| others[1] |
1055 |
1 |
|
T3 |
1 |
|
T4 |
5 |
|
T24 |
1 |
| others[2] |
996 |
1 |
|
T4 |
2 |
|
T17 |
1 |
|
T23 |
1 |
| others[3] |
1765 |
1 |
|
T4 |
1 |
|
T8 |
1 |
|
T16 |
1 |
| false |
600 |
1 |
|
T9 |
1 |
|
T99 |
2 |
|
T57 |
1 |
| true |
1371 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T33 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T112 |
9 |
|
T114 |
9 |
|
T377 |
1 |
| others[1] |
230 |
1 |
|
T33 |
1 |
|
T34 |
1 |
|
T112 |
14 |
| others[2] |
222 |
1 |
|
T5 |
1 |
|
T112 |
8 |
|
T114 |
7 |
| others[3] |
384 |
1 |
|
T8 |
1 |
|
T24 |
1 |
|
T51 |
1 |
| false |
127 |
1 |
|
T118 |
1 |
|
T112 |
2 |
|
T31 |
1 |
| true |
5693 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T16 |
1 |
|
T127 |
1 |
|
T130 |
1 |
| others[1] |
209 |
1 |
|
T33 |
1 |
|
T112 |
11 |
|
T114 |
10 |
| others[2] |
232 |
1 |
|
T118 |
1 |
|
T50 |
1 |
|
T61 |
1 |
| others[3] |
375 |
1 |
|
T41 |
1 |
|
T112 |
14 |
|
T305 |
1 |
| false |
117 |
1 |
|
T112 |
4 |
|
T114 |
7 |
|
T375 |
1 |
| true |
5723 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1305 |
1 |
|
T4 |
2 |
|
T16 |
1 |
|
T9 |
1 |
| others[1] |
1202 |
1 |
|
T4 |
3 |
|
T17 |
1 |
|
T99 |
21 |
| others[2] |
1246 |
1 |
|
T4 |
1 |
|
T9 |
1 |
|
T182 |
1 |
| others[3] |
2041 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T9 |
3 |
| false |
639 |
1 |
|
T4 |
2 |
|
T9 |
2 |
|
T99 |
5 |
| true |
439 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |