Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1242 |
1 |
|
T4 |
2 |
|
T54 |
1 |
|
T99 |
25 |
| others[1] |
1202 |
1 |
|
T4 |
2 |
|
T9 |
1 |
|
T45 |
1 |
| others[2] |
1234 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T9 |
4 |
| others[3] |
2081 |
1 |
|
T3 |
1 |
|
T4 |
5 |
|
T9 |
2 |
| false |
690 |
1 |
|
T4 |
1 |
|
T55 |
1 |
|
T99 |
15 |
| true |
423 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
121 |
1 |
|
T130 |
1 |
|
T112 |
3 |
|
T114 |
2 |
| others[1] |
93 |
1 |
|
T112 |
2 |
|
T114 |
3 |
|
T380 |
1 |
| others[2] |
93 |
1 |
|
T41 |
1 |
|
T112 |
1 |
|
T114 |
4 |
| others[3] |
170 |
1 |
|
T41 |
1 |
|
T110 |
1 |
|
T112 |
10 |
| false |
46 |
1 |
|
T114 |
1 |
|
T81 |
4 |
|
T383 |
1 |
| true |
6349 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
255 |
1 |
|
T55 |
1 |
|
T25 |
1 |
|
T26 |
1 |
| others[1] |
235 |
1 |
|
T130 |
1 |
|
T112 |
11 |
|
T114 |
11 |
| others[2] |
232 |
1 |
|
T16 |
1 |
|
T127 |
1 |
|
T112 |
8 |
| others[3] |
378 |
1 |
|
T34 |
1 |
|
T50 |
1 |
|
T27 |
1 |
| false |
151 |
1 |
|
T23 |
1 |
|
T111 |
1 |
|
T112 |
7 |
| true |
5621 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1095 |
1 |
|
T2 |
1 |
|
T4 |
2 |
|
T8 |
1 |
| others[1] |
1039 |
1 |
|
T4 |
2 |
|
T16 |
1 |
|
T99 |
9 |
| others[2] |
1054 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T9 |
3 |
| others[3] |
1743 |
1 |
|
T4 |
3 |
|
T9 |
2 |
|
T17 |
1 |
| false |
563 |
1 |
|
T4 |
2 |
|
T45 |
1 |
|
T99 |
6 |
| true |
1378 |
1 |
|
T5 |
1 |
|
T33 |
1 |
|
T23 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
243 |
1 |
|
T8 |
1 |
|
T127 |
1 |
|
T112 |
14 |
| others[1] |
224 |
1 |
|
T41 |
1 |
|
T34 |
1 |
|
T50 |
1 |
| others[2] |
246 |
1 |
|
T25 |
1 |
|
T112 |
12 |
|
T305 |
1 |
| others[3] |
385 |
1 |
|
T5 |
1 |
|
T27 |
1 |
|
T112 |
17 |
| false |
110 |
1 |
|
T112 |
5 |
|
T114 |
2 |
|
T384 |
1 |
| true |
5664 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T118 |
1 |
|
T112 |
6 |
|
T114 |
11 |
| others[1] |
233 |
1 |
|
T130 |
1 |
|
T112 |
13 |
|
T305 |
1 |
| others[2] |
206 |
1 |
|
T110 |
1 |
|
T112 |
10 |
|
T114 |
6 |
| others[3] |
383 |
1 |
|
T5 |
1 |
|
T33 |
1 |
|
T34 |
1 |
| false |
98 |
1 |
|
T41 |
1 |
|
T112 |
5 |
|
T114 |
5 |
| true |
5732 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1278 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T99 |
12 |
| others[1] |
1216 |
1 |
|
T4 |
4 |
|
T9 |
1 |
|
T17 |
1 |
| others[2] |
1190 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T16 |
1 |
| others[3] |
2098 |
1 |
|
T4 |
2 |
|
T9 |
1 |
|
T24 |
1 |
| false |
642 |
1 |
|
T4 |
1 |
|
T99 |
12 |
|
T67 |
1 |
| true |
448 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1251 |
1 |
|
T4 |
2 |
|
T9 |
1 |
|
T99 |
16 |
| others[1] |
1177 |
1 |
|
T4 |
2 |
|
T9 |
2 |
|
T55 |
1 |
| others[2] |
1270 |
1 |
|
T4 |
2 |
|
T16 |
1 |
|
T9 |
1 |
| others[3] |
2079 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T9 |
3 |
| false |
675 |
1 |
|
T4 |
2 |
|
T99 |
13 |
|
T41 |
1 |
| true |
420 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
90 |
1 |
|
T112 |
7 |
|
T377 |
1 |
|
T81 |
3 |
| others[1] |
110 |
1 |
|
T55 |
1 |
|
T112 |
3 |
|
T114 |
6 |
| others[2] |
113 |
1 |
|
T41 |
1 |
|
T112 |
6 |
|
T114 |
2 |
| others[3] |
183 |
1 |
|
T112 |
4 |
|
T305 |
1 |
|
T114 |
5 |
| false |
47 |
1 |
|
T41 |
1 |
|
T112 |
1 |
|
T305 |
1 |
| true |
6329 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T33 |
1 |
|
T24 |
1 |
|
T27 |
1 |
| others[1] |
225 |
1 |
|
T112 |
11 |
|
T114 |
6 |
|
T377 |
1 |
| others[2] |
224 |
1 |
|
T25 |
1 |
|
T61 |
1 |
|
T112 |
9 |
| others[3] |
398 |
1 |
|
T112 |
15 |
|
T114 |
19 |
|
T35 |
1 |
| false |
118 |
1 |
|
T5 |
1 |
|
T118 |
1 |
|
T41 |
2 |
| true |
5668 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1057 |
1 |
|
T4 |
2 |
|
T9 |
1 |
|
T17 |
1 |
| others[1] |
1049 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T16 |
1 |
| others[2] |
1060 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T9 |
2 |
| others[3] |
1762 |
1 |
|
T2 |
1 |
|
T4 |
7 |
|
T9 |
2 |
| false |
553 |
1 |
|
T25 |
1 |
|
T99 |
3 |
|
T21 |
1 |
| true |
1391 |
1 |
|
T8 |
1 |
|
T33 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T55 |
1 |
|
T41 |
1 |
|
T61 |
1 |
| others[1] |
240 |
1 |
|
T8 |
1 |
|
T25 |
1 |
|
T41 |
1 |
| others[2] |
218 |
1 |
|
T112 |
6 |
|
T114 |
11 |
|
T29 |
1 |
| others[3] |
378 |
1 |
|
T110 |
1 |
|
T112 |
19 |
|
T114 |
19 |
| false |
121 |
1 |
|
T5 |
1 |
|
T118 |
1 |
|
T112 |
8 |
| true |
5676 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
207 |
1 |
|
T112 |
9 |
|
T305 |
1 |
|
T114 |
12 |
| others[1] |
219 |
1 |
|
T55 |
1 |
|
T41 |
1 |
|
T112 |
12 |
| others[2] |
182 |
1 |
|
T118 |
1 |
|
T112 |
8 |
|
T114 |
8 |
| others[3] |
384 |
1 |
|
T34 |
1 |
|
T51 |
1 |
|
T110 |
1 |
| false |
111 |
1 |
|
T112 |
10 |
|
T114 |
7 |
|
T81 |
7 |
| true |
5769 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1224 |
1 |
|
T182 |
1 |
|
T99 |
16 |
|
T100 |
1 |
| others[1] |
1276 |
1 |
|
T3 |
1 |
|
T4 |
4 |
|
T9 |
5 |
| others[2] |
1230 |
1 |
|
T4 |
3 |
|
T9 |
1 |
|
T99 |
18 |
| others[3] |
2025 |
1 |
|
T4 |
3 |
|
T9 |
1 |
|
T54 |
1 |
| false |
663 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T99 |
11 |
| true |
454 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1233 |
1 |
|
T4 |
2 |
|
T9 |
3 |
|
T45 |
1 |
| others[1] |
1241 |
1 |
|
T4 |
2 |
|
T9 |
2 |
|
T55 |
1 |
| others[2] |
1264 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T16 |
1 |
| others[3] |
2022 |
1 |
|
T4 |
4 |
|
T9 |
2 |
|
T62 |
1 |
| false |
675 |
1 |
|
T99 |
6 |
|
T41 |
1 |
|
T67 |
2 |
| true |
437 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
96 |
1 |
|
T41 |
1 |
|
T112 |
1 |
|
T305 |
1 |
| others[1] |
89 |
1 |
|
T112 |
2 |
|
T114 |
3 |
|
T308 |
2 |
| others[2] |
112 |
1 |
|
T41 |
1 |
|
T130 |
1 |
|
T112 |
3 |
| others[3] |
154 |
1 |
|
T5 |
1 |
|
T112 |
7 |
|
T114 |
3 |
| false |
45 |
1 |
|
T112 |
1 |
|
T114 |
2 |
|
T373 |
1 |
| true |
6376 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
276 |
1 |
|
T23 |
1 |
|
T41 |
1 |
|
T127 |
1 |
| others[1] |
249 |
1 |
|
T16 |
1 |
|
T118 |
1 |
|
T25 |
1 |
| others[2] |
207 |
1 |
|
T26 |
1 |
|
T111 |
1 |
|
T112 |
9 |
| others[3] |
387 |
1 |
|
T61 |
1 |
|
T110 |
1 |
|
T128 |
1 |
| false |
128 |
1 |
|
T34 |
1 |
|
T112 |
6 |
|
T114 |
7 |
| true |
5625 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1063 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T9 |
5 |
| others[1] |
1133 |
1 |
|
T2 |
1 |
|
T4 |
3 |
|
T17 |
1 |
| others[2] |
1034 |
1 |
|
T4 |
2 |
|
T54 |
1 |
|
T182 |
1 |
| others[3] |
1706 |
1 |
|
T4 |
3 |
|
T9 |
2 |
|
T24 |
1 |
| false |
562 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T13 |
1 |
| true |
1374 |
1 |
|
T5 |
1 |
|
T8 |
1 |
|
T33 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
236 |
1 |
|
T24 |
1 |
|
T112 |
9 |
|
T114 |
8 |
| others[1] |
227 |
1 |
|
T16 |
1 |
|
T41 |
1 |
|
T51 |
1 |
| others[2] |
231 |
1 |
|
T34 |
1 |
|
T61 |
1 |
|
T111 |
1 |
| others[3] |
388 |
1 |
|
T110 |
1 |
|
T112 |
18 |
|
T114 |
15 |
| false |
121 |
1 |
|
T8 |
1 |
|
T50 |
1 |
|
T27 |
1 |
| true |
5669 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T41 |
1 |
|
T51 |
1 |
|
T130 |
1 |
| others[1] |
219 |
1 |
|
T16 |
1 |
|
T33 |
1 |
|
T112 |
13 |
| others[2] |
222 |
1 |
|
T34 |
1 |
|
T112 |
13 |
|
T114 |
9 |
| others[3] |
381 |
1 |
|
T55 |
1 |
|
T61 |
1 |
|
T110 |
1 |
| false |
112 |
1 |
|
T112 |
5 |
|
T305 |
1 |
|
T114 |
1 |
| true |
5699 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1207 |
1 |
|
T4 |
1 |
|
T9 |
2 |
|
T33 |
1 |
| others[1] |
1283 |
1 |
|
T4 |
2 |
|
T16 |
1 |
|
T9 |
1 |
| others[2] |
1241 |
1 |
|
T4 |
2 |
|
T9 |
2 |
|
T55 |
1 |
| others[3] |
2079 |
1 |
|
T3 |
1 |
|
T4 |
4 |
|
T9 |
1 |
| false |
624 |
1 |
|
T4 |
2 |
|
T9 |
1 |
|
T99 |
6 |
| true |
438 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1178 |
1 |
|
T4 |
2 |
|
T16 |
1 |
|
T9 |
1 |
| others[1] |
1258 |
1 |
|
T4 |
1 |
|
T9 |
2 |
|
T45 |
1 |
| others[2] |
1275 |
1 |
|
T4 |
3 |
|
T9 |
2 |
|
T99 |
24 |
| others[3] |
2124 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T9 |
2 |
| false |
612 |
1 |
|
T4 |
2 |
|
T7 |
1 |
|
T99 |
4 |
| true |
425 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
127 |
1 |
|
T112 |
5 |
|
T114 |
6 |
|
T377 |
1 |
| others[1] |
111 |
1 |
|
T112 |
5 |
|
T114 |
5 |
|
T81 |
12 |
| others[2] |
105 |
1 |
|
T112 |
2 |
|
T114 |
8 |
|
T377 |
1 |
| others[3] |
190 |
1 |
|
T16 |
1 |
|
T41 |
2 |
|
T112 |
9 |
| false |
43 |
1 |
|
T305 |
1 |
|
T114 |
1 |
|
T81 |
1 |
| true |
6296 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T5 |
1 |
|
T24 |
1 |
|
T112 |
9 |
| others[1] |
214 |
1 |
|
T41 |
1 |
|
T50 |
1 |
|
T61 |
1 |
| others[2] |
233 |
1 |
|
T33 |
1 |
|
T25 |
1 |
|
T128 |
1 |
| others[3] |
396 |
1 |
|
T16 |
1 |
|
T130 |
1 |
|
T112 |
21 |
| false |
131 |
1 |
|
T23 |
1 |
|
T112 |
6 |
|
T114 |
3 |
| true |
5657 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1050 |
1 |
|
T2 |
1 |
|
T4 |
2 |
|
T8 |
1 |
| others[1] |
1046 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
| others[2] |
1055 |
1 |
|
T4 |
2 |
|
T17 |
1 |
|
T99 |
11 |
| others[3] |
1794 |
1 |
|
T4 |
5 |
|
T16 |
1 |
|
T9 |
3 |
| false |
565 |
1 |
|
T4 |
1 |
|
T9 |
1 |
|
T45 |
1 |
| true |
1362 |
1 |
|
T13 |
1 |
|
T62 |
1 |
|
T54 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
252 |
1 |
|
T5 |
1 |
|
T51 |
1 |
|
T112 |
16 |
| others[1] |
242 |
1 |
|
T112 |
7 |
|
T305 |
2 |
|
T114 |
4 |
| others[2] |
251 |
1 |
|
T16 |
1 |
|
T33 |
1 |
|
T55 |
1 |
| others[3] |
361 |
1 |
|
T25 |
1 |
|
T41 |
1 |
|
T34 |
1 |
| false |
117 |
1 |
|
T24 |
1 |
|
T112 |
1 |
|
T114 |
5 |
| true |
5649 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T118 |
1 |
|
T41 |
1 |
|
T127 |
1 |
| others[1] |
185 |
1 |
|
T61 |
1 |
|
T112 |
6 |
|
T114 |
15 |
| others[2] |
234 |
1 |
|
T5 |
1 |
|
T55 |
1 |
|
T112 |
11 |
| others[3] |
354 |
1 |
|
T50 |
1 |
|
T112 |
17 |
|
T114 |
12 |
| false |
124 |
1 |
|
T41 |
1 |
|
T112 |
7 |
|
T114 |
7 |
| true |
5755 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1243 |
1 |
|
T4 |
2 |
|
T16 |
1 |
|
T9 |
3 |
| others[1] |
1206 |
1 |
|
T4 |
3 |
|
T9 |
1 |
|
T99 |
17 |
| others[2] |
1311 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T5 |
1 |
| others[3] |
2058 |
1 |
|
T4 |
4 |
|
T9 |
1 |
|
T17 |
1 |
| false |
613 |
1 |
|
T9 |
2 |
|
T7 |
1 |
|
T118 |
1 |
| true |
441 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T33 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
7 |
1 |
|
T177 |
1 |
|
T385 |
1 |
|
T386 |
1 |
| others[1] |
8 |
1 |
|
T157 |
1 |
|
T387 |
1 |
|
T388 |
1 |
| others[2] |
12 |
1 |
|
T40 |
1 |
|
T170 |
1 |
|
T157 |
1 |
| others[3] |
9 |
1 |
|
T72 |
1 |
|
T73 |
1 |
|
T161 |
1 |
| false |
6 |
1 |
|
T389 |
1 |
|
T390 |
1 |
|
T391 |
1 |
| true |
36 |
1 |
|
T1 |
1 |
|
T79 |
1 |
|
T155 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2 |
1 |
|
T392 |
1 |
|
T393 |
1 |
|
- |
- |
| others[1] |
2 |
1 |
|
T394 |
1 |
|
T395 |
1 |
|
- |
- |
| others[2] |
1 |
1 |
|
T396 |
1 |
|
- |
- |
|
- |
- |
| others[3] |
5 |
1 |
|
T185 |
1 |
|
T397 |
1 |
|
T398 |
1 |
| false |
14 |
1 |
|
T399 |
1 |
|
T400 |
1 |
|
T401 |
1 |
| true |
24 |
1 |
|
T6 |
1 |
|
T19 |
1 |
|
T30 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
4 |
1 |
|
T402 |
1 |
|
T403 |
1 |
|
T404 |
1 |
| others[1] |
4 |
1 |
|
T405 |
1 |
|
T406 |
1 |
|
T407 |
1 |
| others[2] |
3 |
1 |
|
T401 |
1 |
|
T408 |
1 |
|
T409 |
1 |
| others[3] |
2 |
1 |
|
T395 |
1 |
|
T410 |
1 |
|
- |
- |
| false |
6 |
1 |
|
T6 |
1 |
|
T245 |
1 |
|
T411 |
1 |
| true |
29 |
1 |
|
T19 |
1 |
|
T30 |
1 |
|
T185 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |