Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9817 |
1 |
|
T4 |
4 |
|
T9 |
1 |
|
T17 |
1 |
| others[1] |
824 |
1 |
|
T4 |
1 |
|
T9 |
1 |
|
T23 |
1 |
| others[2] |
765 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T16 |
1 |
| others[3] |
1302 |
1 |
|
T4 |
2 |
|
T9 |
3 |
|
T54 |
1 |
| false |
413 |
1 |
|
T4 |
2 |
|
T38 |
1 |
|
T67 |
2 |
| true |
529 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2288 |
1 |
|
T4 |
3 |
|
T9 |
2 |
|
T44 |
25 |
| others[1] |
2383 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T16 |
1 |
| others[2] |
2335 |
1 |
|
T4 |
3 |
|
T5 |
1 |
|
T9 |
2 |
| others[3] |
3775 |
1 |
|
T4 |
3 |
|
T9 |
2 |
|
T60 |
1 |
| false |
1224 |
1 |
|
T4 |
1 |
|
T9 |
1 |
|
T17 |
1 |
| true |
1645 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T33 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9260 |
1 |
|
T45 |
1 |
|
T60 |
2 |
|
T44 |
106 |
| others[1] |
278 |
1 |
|
T55 |
1 |
|
T38 |
1 |
|
T112 |
8 |
| others[2] |
272 |
1 |
|
T5 |
1 |
|
T16 |
1 |
|
T17 |
1 |
| others[3] |
429 |
1 |
|
T3 |
1 |
|
T8 |
1 |
|
T24 |
1 |
| false |
138 |
1 |
|
T25 |
1 |
|
T41 |
1 |
|
T127 |
1 |
| true |
3273 |
1 |
|
T2 |
1 |
|
T4 |
11 |
|
T9 |
7 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9463 |
1 |
|
T4 |
1 |
|
T9 |
2 |
|
T45 |
1 |
| others[1] |
500 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T5 |
1 |
| others[2] |
453 |
1 |
|
T4 |
1 |
|
T23 |
1 |
|
T100 |
1 |
| others[3] |
817 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
| false |
230 |
1 |
|
T9 |
1 |
|
T67 |
1 |
|
T128 |
1 |
| true |
2187 |
1 |
|
T4 |
7 |
|
T8 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9267 |
1 |
|
T33 |
1 |
|
T24 |
1 |
|
T60 |
2 |
| others[1] |
272 |
1 |
|
T7 |
1 |
|
T112 |
10 |
|
T114 |
16 |
| others[2] |
257 |
1 |
|
T16 |
1 |
|
T41 |
1 |
|
T111 |
1 |
| others[3] |
430 |
1 |
|
T57 |
1 |
|
T100 |
1 |
|
T127 |
1 |
| false |
137 |
1 |
|
T112 |
6 |
|
T305 |
1 |
|
T114 |
4 |
| true |
3287 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9261 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T60 |
2 |
| others[1] |
233 |
1 |
|
T376 |
1 |
|
T101 |
1 |
|
T112 |
11 |
| others[2] |
231 |
1 |
|
T21 |
1 |
|
T100 |
1 |
|
T112 |
8 |
| others[3] |
453 |
1 |
|
T182 |
1 |
|
T57 |
1 |
|
T61 |
1 |
| false |
128 |
1 |
|
T45 |
1 |
|
T34 |
1 |
|
T112 |
9 |
| true |
3344 |
1 |
|
T2 |
1 |
|
T4 |
11 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9819 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T9 |
3 |
| others[1] |
782 |
1 |
|
T4 |
1 |
|
T9 |
2 |
|
T17 |
1 |
| others[2] |
826 |
1 |
|
T4 |
1 |
|
T67 |
5 |
|
T107 |
1 |
| others[3] |
1332 |
1 |
|
T4 |
3 |
|
T9 |
2 |
|
T33 |
1 |
| false |
392 |
1 |
|
T16 |
1 |
|
T50 |
1 |
|
T109 |
8 |
| true |
499 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9772 |
1 |
|
T4 |
1 |
|
T9 |
2 |
|
T60 |
2 |
| others[1] |
807 |
1 |
|
T4 |
2 |
|
T9 |
2 |
|
T7 |
1 |
| others[2] |
770 |
1 |
|
T3 |
1 |
|
T4 |
4 |
|
T9 |
1 |
| others[3] |
1342 |
1 |
|
T4 |
3 |
|
T9 |
1 |
|
T182 |
1 |
| false |
392 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T9 |
1 |
| true |
539 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2333 |
1 |
|
T4 |
2 |
|
T9 |
2 |
|
T60 |
1 |
| others[1] |
2361 |
1 |
|
T4 |
4 |
|
T9 |
3 |
|
T44 |
24 |
| others[2] |
2273 |
1 |
|
T4 |
3 |
|
T9 |
1 |
|
T45 |
1 |
| others[3] |
3896 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T5 |
1 |
| false |
1209 |
1 |
|
T9 |
1 |
|
T44 |
10 |
|
T99 |
8 |
| true |
1550 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T33 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9251 |
1 |
|
T5 |
1 |
|
T45 |
1 |
|
T60 |
2 |
| others[1] |
261 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T23 |
1 |
| others[2] |
295 |
1 |
|
T118 |
1 |
|
T101 |
1 |
|
T112 |
11 |
| others[3] |
464 |
1 |
|
T8 |
1 |
|
T24 |
1 |
|
T21 |
1 |
| false |
133 |
1 |
|
T182 |
1 |
|
T110 |
1 |
|
T112 |
3 |
| true |
3218 |
1 |
|
T2 |
1 |
|
T4 |
11 |
|
T9 |
7 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9511 |
1 |
|
T4 |
2 |
|
T60 |
2 |
|
T44 |
106 |
| others[1] |
456 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T9 |
1 |
| others[2] |
477 |
1 |
|
T4 |
2 |
|
T16 |
1 |
|
T25 |
1 |
| others[3] |
750 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T9 |
2 |
| false |
242 |
1 |
|
T4 |
1 |
|
T8 |
1 |
|
T24 |
1 |
| true |
2186 |
1 |
|
T4 |
4 |
|
T5 |
1 |
|
T9 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9268 |
1 |
|
T33 |
1 |
|
T45 |
1 |
|
T60 |
2 |
| others[1] |
252 |
1 |
|
T16 |
1 |
|
T128 |
1 |
|
T112 |
14 |
| others[2] |
273 |
1 |
|
T3 |
1 |
|
T55 |
1 |
|
T376 |
1 |
| others[3] |
430 |
1 |
|
T7 |
1 |
|
T51 |
1 |
|
T112 |
16 |
| false |
140 |
1 |
|
T112 |
7 |
|
T114 |
7 |
|
T384 |
1 |
| true |
3259 |
1 |
|
T2 |
1 |
|
T4 |
11 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9250 |
1 |
|
T60 |
2 |
|
T44 |
106 |
|
T99 |
100 |
| others[1] |
254 |
1 |
|
T16 |
1 |
|
T45 |
1 |
|
T41 |
1 |
| others[2] |
270 |
1 |
|
T376 |
1 |
|
T131 |
1 |
|
T112 |
12 |
| others[3] |
430 |
1 |
|
T33 |
1 |
|
T41 |
1 |
|
T110 |
1 |
| false |
130 |
1 |
|
T55 |
1 |
|
T112 |
3 |
|
T114 |
6 |
| true |
3288 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9789 |
1 |
|
T4 |
1 |
|
T9 |
2 |
|
T45 |
1 |
| others[1] |
819 |
1 |
|
T4 |
2 |
|
T9 |
2 |
|
T17 |
1 |
| others[2] |
828 |
1 |
|
T4 |
1 |
|
T55 |
1 |
|
T21 |
1 |
| others[3] |
1290 |
1 |
|
T4 |
5 |
|
T9 |
2 |
|
T41 |
1 |
| false |
381 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T16 |
1 |
| true |
515 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9786 |
1 |
|
T4 |
2 |
|
T16 |
1 |
|
T60 |
2 |
| others[1] |
772 |
1 |
|
T4 |
1 |
|
T118 |
1 |
|
T67 |
3 |
| others[2] |
782 |
1 |
|
T4 |
2 |
|
T9 |
5 |
|
T182 |
1 |
| others[3] |
1341 |
1 |
|
T3 |
1 |
|
T4 |
4 |
|
T17 |
1 |
| false |
414 |
1 |
|
T2 |
1 |
|
T4 |
2 |
|
T9 |
2 |
| true |
527 |
1 |
|
T5 |
1 |
|
T8 |
1 |
|
T33 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2387 |
1 |
|
T9 |
2 |
|
T7 |
1 |
|
T44 |
22 |
| others[1] |
2307 |
1 |
|
T4 |
4 |
|
T9 |
1 |
|
T60 |
1 |
| others[2] |
2293 |
1 |
|
T3 |
1 |
|
T4 |
4 |
|
T44 |
15 |
| others[3] |
3935 |
1 |
|
T4 |
3 |
|
T5 |
1 |
|
T9 |
4 |
| false |
1151 |
1 |
|
T17 |
1 |
|
T45 |
1 |
|
T182 |
1 |
| true |
1549 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9264 |
1 |
|
T8 |
1 |
|
T60 |
2 |
|
T118 |
1 |
| others[1] |
305 |
1 |
|
T24 |
1 |
|
T110 |
1 |
|
T128 |
1 |
| others[2] |
270 |
1 |
|
T5 |
1 |
|
T27 |
1 |
|
T112 |
16 |
| others[3] |
466 |
1 |
|
T45 |
1 |
|
T7 |
1 |
|
T376 |
1 |
| false |
145 |
1 |
|
T112 |
5 |
|
T114 |
6 |
|
T227 |
1 |
| true |
3172 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9491 |
1 |
|
T9 |
1 |
|
T60 |
2 |
|
T44 |
106 |
| others[1] |
483 |
1 |
|
T3 |
1 |
|
T33 |
1 |
|
T23 |
1 |
| others[2] |
460 |
1 |
|
T8 |
1 |
|
T9 |
1 |
|
T41 |
1 |
| others[3] |
805 |
1 |
|
T4 |
2 |
|
T9 |
2 |
|
T376 |
1 |
| false |
260 |
1 |
|
T4 |
1 |
|
T9 |
1 |
|
T62 |
1 |
| true |
2123 |
1 |
|
T2 |
1 |
|
T4 |
8 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9262 |
1 |
|
T17 |
1 |
|
T7 |
1 |
|
T60 |
2 |
| others[1] |
270 |
1 |
|
T16 |
1 |
|
T55 |
1 |
|
T41 |
1 |
| others[2] |
261 |
1 |
|
T3 |
1 |
|
T182 |
1 |
|
T127 |
1 |
| others[3] |
480 |
1 |
|
T8 |
1 |
|
T33 |
1 |
|
T21 |
1 |
| false |
140 |
1 |
|
T118 |
1 |
|
T112 |
1 |
|
T114 |
2 |
| true |
3209 |
1 |
|
T2 |
1 |
|
T4 |
11 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9254 |
1 |
|
T5 |
1 |
|
T60 |
2 |
|
T44 |
106 |
| others[1] |
263 |
1 |
|
T45 |
1 |
|
T7 |
1 |
|
T41 |
1 |
| others[2] |
250 |
1 |
|
T55 |
1 |
|
T118 |
1 |
|
T376 |
1 |
| others[3] |
398 |
1 |
|
T17 |
1 |
|
T61 |
1 |
|
T101 |
1 |
| false |
135 |
1 |
|
T16 |
1 |
|
T131 |
1 |
|
T112 |
4 |
| true |
3322 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9838 |
1 |
|
T4 |
3 |
|
T5 |
1 |
|
T9 |
3 |
| others[1] |
767 |
1 |
|
T4 |
3 |
|
T16 |
1 |
|
T54 |
1 |
| others[2] |
779 |
1 |
|
T4 |
1 |
|
T67 |
3 |
|
T109 |
15 |
| others[3] |
1324 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T9 |
4 |
| false |
409 |
1 |
|
T4 |
1 |
|
T38 |
1 |
|
T109 |
8 |
| true |
505 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T33 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9794 |
1 |
|
T3 |
1 |
|
T4 |
5 |
|
T24 |
1 |
| others[1] |
800 |
1 |
|
T2 |
1 |
|
T9 |
2 |
|
T17 |
1 |
| others[2] |
757 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T9 |
1 |
| others[3] |
1305 |
1 |
|
T4 |
3 |
|
T9 |
4 |
|
T45 |
1 |
| false |
440 |
1 |
|
T4 |
2 |
|
T67 |
1 |
|
T109 |
8 |
| true |
526 |
1 |
|
T5 |
1 |
|
T8 |
1 |
|
T33 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2261 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T9 |
2 |
| others[1] |
2292 |
1 |
|
T4 |
3 |
|
T9 |
1 |
|
T33 |
1 |
| others[2] |
2415 |
1 |
|
T4 |
1 |
|
T9 |
3 |
|
T44 |
22 |
| others[3] |
3888 |
1 |
|
T4 |
3 |
|
T5 |
1 |
|
T9 |
1 |
| false |
1200 |
1 |
|
T4 |
1 |
|
T44 |
8 |
|
T99 |
8 |
| true |
1566 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9254 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T23 |
1 |
| others[1] |
308 |
1 |
|
T16 |
1 |
|
T41 |
1 |
|
T128 |
1 |
| others[2] |
261 |
1 |
|
T118 |
1 |
|
T127 |
1 |
|
T101 |
1 |
| others[3] |
454 |
1 |
|
T8 |
1 |
|
T45 |
1 |
|
T376 |
1 |
| false |
133 |
1 |
|
T57 |
1 |
|
T111 |
1 |
|
T112 |
4 |
| true |
3212 |
1 |
|
T2 |
1 |
|
T4 |
11 |
|
T9 |
7 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9477 |
1 |
|
T4 |
4 |
|
T9 |
2 |
|
T13 |
1 |
| others[1] |
475 |
1 |
|
T5 |
1 |
|
T25 |
1 |
|
T71 |
1 |
| others[2] |
467 |
1 |
|
T4 |
2 |
|
T8 |
1 |
|
T9 |
1 |
| others[3] |
785 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T41 |
1 |
| false |
230 |
1 |
|
T9 |
1 |
|
T178 |
1 |
|
T24 |
1 |
| true |
2188 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9270 |
1 |
|
T3 |
1 |
|
T45 |
1 |
|
T60 |
2 |
| others[1] |
256 |
1 |
|
T24 |
1 |
|
T112 |
7 |
|
T305 |
1 |
| others[2] |
266 |
1 |
|
T25 |
1 |
|
T61 |
1 |
|
T131 |
1 |
| others[3] |
453 |
1 |
|
T5 |
1 |
|
T55 |
1 |
|
T34 |
1 |
| false |
126 |
1 |
|
T111 |
1 |
|
T112 |
2 |
|
T114 |
9 |
| true |
3251 |
1 |
|
T2 |
1 |
|
T4 |
11 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9230 |
1 |
|
T5 |
1 |
|
T60 |
2 |
|
T44 |
106 |
| others[1] |
264 |
1 |
|
T38 |
1 |
|
T41 |
1 |
|
T127 |
1 |
| others[2] |
256 |
1 |
|
T16 |
1 |
|
T61 |
1 |
|
T112 |
18 |
| others[3] |
426 |
1 |
|
T45 |
1 |
|
T55 |
1 |
|
T21 |
1 |
| false |
143 |
1 |
|
T182 |
1 |
|
T128 |
1 |
|
T112 |
5 |
| true |
3303 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9838 |
1 |
|
T4 |
3 |
|
T60 |
2 |
|
T55 |
1 |
| others[1] |
823 |
1 |
|
T9 |
1 |
|
T118 |
1 |
|
T376 |
1 |
| others[2] |
743 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T16 |
1 |
| others[3] |
1334 |
1 |
|
T4 |
3 |
|
T9 |
1 |
|
T17 |
1 |
| false |
377 |
1 |
|
T4 |
2 |
|
T9 |
2 |
|
T38 |
1 |
| true |
507 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9832 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T9 |
2 |
| others[1] |
803 |
1 |
|
T4 |
4 |
|
T9 |
1 |
|
T17 |
1 |
| others[2] |
758 |
1 |
|
T4 |
1 |
|
T9 |
2 |
|
T21 |
1 |
| others[3] |
1299 |
1 |
|
T4 |
5 |
|
T16 |
1 |
|
T9 |
2 |
| false |
402 |
1 |
|
T4 |
1 |
|
T23 |
1 |
|
T67 |
2 |
| true |
528 |
1 |
|
T5 |
1 |
|
T8 |
1 |
|
T33 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2355 |
1 |
|
T4 |
5 |
|
T17 |
1 |
|
T60 |
1 |
| others[1] |
2370 |
1 |
|
T4 |
2 |
|
T9 |
3 |
|
T7 |
1 |
| others[2] |
2310 |
1 |
|
T4 |
1 |
|
T9 |
1 |
|
T33 |
1 |
| others[3] |
3861 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T9 |
2 |
| false |
1199 |
1 |
|
T9 |
1 |
|
T45 |
1 |
|
T44 |
7 |
| true |
1527 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9267 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T60 |
2 |
| others[1] |
290 |
1 |
|
T182 |
1 |
|
T55 |
1 |
|
T112 |
11 |
| others[2] |
290 |
1 |
|
T17 |
1 |
|
T33 |
1 |
|
T21 |
1 |
| others[3] |
471 |
1 |
|
T100 |
1 |
|
T26 |
1 |
|
T111 |
1 |
| false |
132 |
1 |
|
T8 |
1 |
|
T41 |
1 |
|
T110 |
1 |
| true |
3172 |
1 |
|
T2 |
1 |
|
T4 |
11 |
|
T5 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |