Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9471 |
1 |
|
T4 |
1 |
|
T9 |
2 |
|
T178 |
1 |
| others[1] |
502 |
1 |
|
T24 |
1 |
|
T55 |
1 |
|
T118 |
1 |
| others[2] |
432 |
1 |
|
T4 |
1 |
|
T9 |
1 |
|
T13 |
1 |
| others[3] |
796 |
1 |
|
T4 |
2 |
|
T16 |
1 |
|
T45 |
1 |
| false |
246 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T9 |
1 |
| true |
2175 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9254 |
1 |
|
T8 |
1 |
|
T60 |
2 |
|
T44 |
106 |
| others[1] |
268 |
1 |
|
T17 |
1 |
|
T41 |
1 |
|
T112 |
8 |
| others[2] |
258 |
1 |
|
T16 |
1 |
|
T7 |
1 |
|
T128 |
1 |
| others[3] |
458 |
1 |
|
T3 |
1 |
|
T33 |
1 |
|
T45 |
1 |
| false |
140 |
1 |
|
T38 |
1 |
|
T110 |
1 |
|
T112 |
8 |
| true |
3244 |
1 |
|
T2 |
1 |
|
T4 |
11 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9281 |
1 |
|
T60 |
2 |
|
T55 |
1 |
|
T44 |
106 |
| others[1] |
262 |
1 |
|
T182 |
1 |
|
T41 |
1 |
|
T112 |
13 |
| others[2] |
227 |
1 |
|
T110 |
1 |
|
T112 |
12 |
|
T114 |
13 |
| others[3] |
399 |
1 |
|
T3 |
1 |
|
T33 |
1 |
|
T118 |
1 |
| false |
157 |
1 |
|
T45 |
1 |
|
T112 |
10 |
|
T412 |
1 |
| true |
3296 |
1 |
|
T2 |
1 |
|
T4 |
11 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9830 |
1 |
|
T4 |
3 |
|
T16 |
1 |
|
T13 |
1 |
| others[1] |
772 |
1 |
|
T9 |
3 |
|
T45 |
1 |
|
T67 |
3 |
| others[2] |
795 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T9 |
1 |
| others[3] |
1300 |
1 |
|
T4 |
6 |
|
T9 |
2 |
|
T17 |
1 |
| false |
407 |
1 |
|
T9 |
1 |
|
T21 |
1 |
|
T109 |
6 |
| true |
518 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9770 |
1 |
|
T4 |
1 |
|
T9 |
2 |
|
T60 |
2 |
| others[1] |
742 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T9 |
1 |
| others[2] |
794 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T9 |
2 |
| others[3] |
1384 |
1 |
|
T4 |
2 |
|
T9 |
2 |
|
T17 |
1 |
| false |
409 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T13 |
1 |
| true |
523 |
1 |
|
T5 |
1 |
|
T8 |
1 |
|
T33 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2336 |
1 |
|
T4 |
2 |
|
T33 |
1 |
|
T44 |
26 |
| others[1] |
2332 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T9 |
3 |
| others[2] |
2323 |
1 |
|
T4 |
3 |
|
T9 |
1 |
|
T60 |
1 |
| others[3] |
3865 |
1 |
|
T4 |
5 |
|
T5 |
1 |
|
T9 |
1 |
| false |
1220 |
1 |
|
T9 |
2 |
|
T7 |
1 |
|
T44 |
7 |
| true |
1546 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9285 |
1 |
|
T60 |
2 |
|
T44 |
106 |
|
T99 |
100 |
| others[1] |
256 |
1 |
|
T45 |
1 |
|
T376 |
1 |
|
T34 |
1 |
| others[2] |
271 |
1 |
|
T16 |
1 |
|
T38 |
1 |
|
T41 |
1 |
| others[3] |
449 |
1 |
|
T101 |
1 |
|
T131 |
1 |
|
T112 |
15 |
| false |
148 |
1 |
|
T23 |
1 |
|
T110 |
1 |
|
T112 |
8 |
| true |
3213 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9452 |
1 |
|
T4 |
1 |
|
T9 |
1 |
|
T60 |
2 |
| others[1] |
438 |
1 |
|
T4 |
3 |
|
T9 |
2 |
|
T62 |
1 |
| others[2] |
472 |
1 |
|
T4 |
1 |
|
T8 |
1 |
|
T9 |
3 |
| others[3] |
733 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T7 |
1 |
| false |
261 |
1 |
|
T4 |
2 |
|
T67 |
2 |
|
T109 |
3 |
| true |
2266 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9257 |
1 |
|
T8 |
1 |
|
T60 |
2 |
|
T55 |
1 |
| others[1] |
254 |
1 |
|
T16 |
1 |
|
T110 |
1 |
|
T112 |
10 |
| others[2] |
258 |
1 |
|
T3 |
1 |
|
T41 |
1 |
|
T112 |
14 |
| others[3] |
451 |
1 |
|
T5 |
1 |
|
T57 |
1 |
|
T50 |
1 |
| false |
151 |
1 |
|
T17 |
1 |
|
T38 |
1 |
|
T61 |
1 |
| true |
3251 |
1 |
|
T2 |
1 |
|
T4 |
11 |
|
T9 |
7 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9233 |
1 |
|
T17 |
1 |
|
T60 |
2 |
|
T44 |
106 |
| others[1] |
265 |
1 |
|
T16 |
1 |
|
T38 |
1 |
|
T101 |
1 |
| others[2] |
252 |
1 |
|
T55 |
1 |
|
T21 |
1 |
|
T376 |
1 |
| others[3] |
419 |
1 |
|
T41 |
1 |
|
T34 |
1 |
|
T51 |
1 |
| false |
140 |
1 |
|
T112 |
6 |
|
T114 |
8 |
|
T81 |
5 |
| true |
3313 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9840 |
1 |
|
T3 |
1 |
|
T4 |
5 |
|
T9 |
1 |
| others[1] |
752 |
1 |
|
T4 |
1 |
|
T9 |
1 |
|
T38 |
1 |
| others[2] |
790 |
1 |
|
T4 |
1 |
|
T9 |
5 |
|
T45 |
1 |
| others[3] |
1309 |
1 |
|
T4 |
3 |
|
T16 |
1 |
|
T17 |
1 |
| false |
430 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T100 |
1 |
| true |
501 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9803 |
1 |
|
T4 |
1 |
|
T9 |
2 |
|
T45 |
1 |
| others[1] |
792 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T9 |
1 |
| others[2] |
780 |
1 |
|
T4 |
2 |
|
T9 |
2 |
|
T55 |
1 |
| others[3] |
1327 |
1 |
|
T4 |
5 |
|
T16 |
1 |
|
T9 |
2 |
| false |
398 |
1 |
|
T4 |
1 |
|
T41 |
1 |
|
T100 |
1 |
| true |
522 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2380 |
1 |
|
T4 |
3 |
|
T9 |
2 |
|
T45 |
1 |
| others[1] |
2307 |
1 |
|
T4 |
3 |
|
T9 |
1 |
|
T17 |
1 |
| others[2] |
2261 |
1 |
|
T9 |
1 |
|
T7 |
1 |
|
T182 |
1 |
| others[3] |
3939 |
1 |
|
T3 |
1 |
|
T4 |
5 |
|
T9 |
2 |
| false |
1226 |
1 |
|
T9 |
1 |
|
T33 |
1 |
|
T44 |
11 |
| true |
1509 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9269 |
1 |
|
T60 |
2 |
|
T182 |
1 |
|
T55 |
1 |
| others[1] |
268 |
1 |
|
T33 |
1 |
|
T118 |
1 |
|
T38 |
1 |
| others[2] |
270 |
1 |
|
T5 |
1 |
|
T16 |
1 |
|
T24 |
1 |
| others[3] |
462 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T7 |
1 |
| false |
158 |
1 |
|
T130 |
1 |
|
T112 |
4 |
|
T114 |
5 |
| true |
3195 |
1 |
|
T2 |
1 |
|
T4 |
11 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9452 |
1 |
|
T4 |
1 |
|
T9 |
1 |
|
T60 |
2 |
| others[1] |
476 |
1 |
|
T4 |
1 |
|
T177 |
1 |
|
T41 |
1 |
| others[2] |
437 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
| others[3] |
808 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T9 |
1 |
| false |
220 |
1 |
|
T4 |
1 |
|
T9 |
1 |
|
T25 |
1 |
| true |
2229 |
1 |
|
T2 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9271 |
1 |
|
T5 |
1 |
|
T60 |
2 |
|
T44 |
106 |
| others[1] |
257 |
1 |
|
T17 |
1 |
|
T182 |
1 |
|
T118 |
1 |
| others[2] |
256 |
1 |
|
T3 |
1 |
|
T33 |
1 |
|
T24 |
1 |
| others[3] |
421 |
1 |
|
T16 |
1 |
|
T45 |
1 |
|
T21 |
1 |
| false |
148 |
1 |
|
T55 |
1 |
|
T51 |
1 |
|
T112 |
7 |
| true |
3269 |
1 |
|
T2 |
1 |
|
T4 |
11 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9252 |
1 |
|
T16 |
1 |
|
T60 |
2 |
|
T182 |
1 |
| others[1] |
256 |
1 |
|
T17 |
1 |
|
T61 |
1 |
|
T130 |
1 |
| others[2] |
239 |
1 |
|
T55 |
1 |
|
T50 |
1 |
|
T112 |
10 |
| others[3] |
452 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T45 |
1 |
| false |
121 |
1 |
|
T131 |
1 |
|
T112 |
2 |
|
T114 |
5 |
| true |
3302 |
1 |
|
T2 |
1 |
|
T4 |
11 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9805 |
1 |
|
T4 |
2 |
|
T60 |
2 |
|
T44 |
106 |
| others[1] |
759 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T9 |
1 |
| others[2] |
805 |
1 |
|
T4 |
3 |
|
T16 |
1 |
|
T9 |
5 |
| others[3] |
1310 |
1 |
|
T4 |
4 |
|
T9 |
1 |
|
T17 |
1 |
| false |
448 |
1 |
|
T55 |
1 |
|
T50 |
1 |
|
T67 |
2 |
| true |
495 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9768 |
1 |
|
T4 |
2 |
|
T9 |
3 |
|
T13 |
1 |
| others[1] |
775 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T16 |
1 |
| others[2] |
802 |
1 |
|
T4 |
2 |
|
T55 |
1 |
|
T67 |
2 |
| others[3] |
1292 |
1 |
|
T4 |
3 |
|
T9 |
2 |
|
T45 |
1 |
| false |
462 |
1 |
|
T4 |
2 |
|
T178 |
1 |
|
T67 |
3 |
| true |
523 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2286 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T9 |
1 |
| others[1] |
2302 |
1 |
|
T9 |
3 |
|
T45 |
1 |
|
T44 |
24 |
| others[2] |
2341 |
1 |
|
T4 |
3 |
|
T9 |
2 |
|
T60 |
1 |
| others[3] |
3999 |
1 |
|
T4 |
6 |
|
T9 |
1 |
|
T17 |
1 |
| false |
1158 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T60 |
1 |
| true |
1536 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9272 |
1 |
|
T45 |
1 |
|
T60 |
2 |
|
T44 |
106 |
| others[1] |
276 |
1 |
|
T17 |
1 |
|
T55 |
1 |
|
T41 |
1 |
| others[2] |
295 |
1 |
|
T33 |
1 |
|
T25 |
1 |
|
T112 |
9 |
| others[3] |
461 |
1 |
|
T8 |
1 |
|
T61 |
1 |
|
T26 |
1 |
| false |
135 |
1 |
|
T5 |
1 |
|
T24 |
1 |
|
T21 |
1 |
| true |
3183 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9446 |
1 |
|
T9 |
2 |
|
T60 |
2 |
|
T44 |
106 |
| others[1] |
450 |
1 |
|
T4 |
2 |
|
T41 |
1 |
|
T100 |
1 |
| others[2] |
498 |
1 |
|
T5 |
1 |
|
T9 |
1 |
|
T118 |
1 |
| others[3] |
813 |
1 |
|
T4 |
3 |
|
T9 |
2 |
|
T13 |
1 |
| false |
230 |
1 |
|
T178 |
1 |
|
T7 |
1 |
|
T55 |
1 |
| true |
2185 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9246 |
1 |
|
T60 |
2 |
|
T44 |
106 |
|
T99 |
100 |
| others[1] |
267 |
1 |
|
T182 |
1 |
|
T57 |
1 |
|
T127 |
1 |
| others[2] |
274 |
1 |
|
T24 |
1 |
|
T101 |
1 |
|
T112 |
12 |
| others[3] |
442 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T17 |
1 |
| false |
156 |
1 |
|
T5 |
1 |
|
T45 |
1 |
|
T100 |
1 |
| true |
3237 |
1 |
|
T2 |
1 |
|
T4 |
11 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9249 |
1 |
|
T60 |
2 |
|
T44 |
106 |
|
T99 |
100 |
| others[1] |
233 |
1 |
|
T110 |
1 |
|
T131 |
1 |
|
T112 |
9 |
| others[2] |
235 |
1 |
|
T38 |
1 |
|
T57 |
1 |
|
T100 |
1 |
| others[3] |
431 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T16 |
1 |
| false |
122 |
1 |
|
T112 |
2 |
|
T32 |
1 |
|
T114 |
6 |
| true |
3352 |
1 |
|
T2 |
1 |
|
T4 |
11 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9771 |
1 |
|
T4 |
3 |
|
T9 |
3 |
|
T60 |
2 |
| others[1] |
875 |
1 |
|
T4 |
2 |
|
T9 |
1 |
|
T182 |
1 |
| others[2] |
797 |
1 |
|
T4 |
2 |
|
T5 |
1 |
|
T9 |
1 |
| others[3] |
1279 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T9 |
2 |
| false |
399 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T178 |
1 |
| true |
501 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T33 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |