Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	223737	1		T3	695		T4	9		T5	249
auto[FlashEraseBank]	250696	1		T3	479		T4	2		T5	171

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	265427	1		T4	5		T5	212		T8	1030
auto[FlashOpProgram]	190077	1		T3	1174		T4	3		T5	208
auto[FlashOpErase]	14929	1		T4	3		T16	34		T9	2
auto[FlashOpInvalid]	4000	1		T99	200		T129	200		T113	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	265427	1		T4	5		T5	212		T8	1030
op[FlashOpProgram]	190077	1		T3	1174		T4	3		T5	208
op[FlashOpErase]	14929	1		T4	3		T16	34		T9	2
read_erase_read	771	1		T16	9		T55	5		T19	3
read_prog_read	1302	1		T5	2		T16	20		T23	35

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	337421	1		T3	865		T4	11		T5	288
auto[FlashPartInfo]	132962	1		T3	309		T5	130		T8	358
auto[FlashPartInfo1]	913	1		T21	17		T38	3		T34	3
auto[FlashPartInfo2]	3137	1		T5	2		T23	1		T24	45

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	202756	1		T4	5		T5	156		T8	672
auto[FlashPartData]	auto[FlashOpProgram]	127083	1		T3	865		T4	3		T5	132
auto[FlashPartData]	auto[FlashOpErase]	3668	1		T4	3		T16	33		T9	2
auto[FlashPartData]	auto[FlashOpInvalid]	3914	1		T99	198		T129	200		T113	192
auto[FlashPartInfo]	auto[FlashOpRead]	59975	1		T5	55		T8	358		T16	1
auto[FlashPartInfo]	auto[FlashOpProgram]	61738	1		T3	309		T5	75		T16	2
auto[FlashPartInfo]	auto[FlashOpErase]	11177	1		T16	1		T6	16		T177	2
auto[FlashPartInfo]	auto[FlashOpInvalid]	72	1		T99	2		T113	6		T414	6
auto[FlashPartInfo1]	auto[FlashOpRead]	747	1		T21	17		T38	3		T34	3
auto[FlashPartInfo1]	auto[FlashOpProgram]	162	1		T82	1		T65	32		T83	32
auto[FlashPartInfo1]	auto[FlashOpErase]	2	1		T82	1		T415	1		-	-
auto[FlashPartInfo1]	auto[FlashOpInvalid]	2	1		T82	2		-	-		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1949	1		T5	1		T23	1		T24	45
auto[FlashPartInfo2]	auto[FlashOpProgram]	1094	1		T5	1		T57	8		T50	7
auto[FlashPartInfo2]	auto[FlashOpErase]	82	1		T113	1		T416	1		T120	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	12	1		T113	2		T416	2		T132	2