Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.48	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	4	28	87.50

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	4	28	87.50	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29041	1		T4	5		T16	24		T55	24
auto[1]	41	1		T27	18		T333	3		T334	2
auto[2]	127	1		T26	1		T115	45		T145	8
auto[3]	369	1		T25	3		T111	1		T35	1

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7431	1		T4	2		T16	6		T55	6
evic_idx[1]	7417	1		T4	1		T16	6		T55	6
evic_idx[2]	7370	1		T4	1		T16	6		T55	6
evic_idx[3]	7360	1		T4	1		T16	6		T55	6

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	28474	1		T44	304		T99	400		T27	18
evic_op[2]	448	1		T4	1		T25	3		T26	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	4	28	87.50	4

Automatically Generated Cross Bins for evic_all_cross

Element holes

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
*	[evic_op[1]]	[auto[2]]	--	--	4

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7044	1		T44	76		T99	100		T129	100
evic_idx[0]	evic_op[1]	auto[1]	8	1		T27	8		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	106	1		T335	10		T336	6		T337	36
evic_idx[0]	evic_op[2]	auto[0]	68	1		T4	1		T114	1		T63	4
evic_idx[0]	evic_op[2]	auto[1]	6	1		T333	1		T186	1		T338	1
evic_idx[0]	evic_op[2]	auto[2]	26	1		T115	10		T339	3		T340	5
evic_idx[0]	evic_op[2]	auto[3]	9	1		T25	1		T35	1		T341	1
evic_idx[1]	evic_op[1]	auto[0]	7034	1		T44	76		T99	100		T129	100
evic_idx[1]	evic_op[1]	auto[1]	6	1		T27	5		T342	1		-	-
evic_idx[1]	evic_op[1]	auto[3]	103	1		T335	10		T336	11		T337	33
evic_idx[1]	evic_op[2]	auto[0]	70	1		T114	1		T63	4		T226	1
evic_idx[1]	evic_op[2]	auto[1]	6	1		T333	1		T334	1		T343	1
evic_idx[1]	evic_op[2]	auto[2]	23	1		T115	9		T339	3		T340	3
evic_idx[1]	evic_op[2]	auto[3]	11	1		T25	1		T111	1		T36	1
evic_idx[2]	evic_op[1]	auto[0]	7024	1		T44	76		T99	100		T129	100
evic_idx[2]	evic_op[1]	auto[1]	3	1		T27	2		T342	1		-	-
evic_idx[2]	evic_op[1]	auto[3]	63	1		T335	2		T336	6		T337	22
evic_idx[2]	evic_op[2]	auto[0]	69	1		T114	1		T63	4		T248	4
evic_idx[2]	evic_op[2]	auto[1]	5	1		T334	1		T186	1		T344	1
evic_idx[2]	evic_op[2]	auto[2]	31	1		T115	13		T339	3		T340	4
evic_idx[2]	evic_op[2]	auto[3]	11	1		T345	1		T346	1		T347	1
evic_idx[3]	evic_op[1]	auto[0]	7022	1		T44	76		T99	100		T129	100
evic_idx[3]	evic_op[1]	auto[1]	3	1		T27	3		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	58	1		T335	6		T336	4		T337	19
evic_idx[3]	evic_op[2]	auto[0]	66	1		T114	1		T63	4		T104	1
evic_idx[3]	evic_op[2]	auto[1]	4	1		T333	1		T186	1		T348	1
evic_idx[3]	evic_op[2]	auto[2]	35	1		T26	1		T115	13		T339	3
evic_idx[3]	evic_op[2]	auto[3]	8	1		T25	1		T349	1		T341	1