Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	34816	1		T207	2923		T327	1831		T328	9134
rd_lvl[2]	32561	1		T21	5864		T207	1623		T327	1648
rd_lvl[3]	7062	1		T8	1355		T21	472		T207	484
rd_lvl[4]	30808	1		T8	3253		T329	2164		T207	927
rd_lvl[5]	18764	1		T8	353		T329	1012		T207	764
rd_lvl[6]	12757	1		T205	1119		T207	5		T208	663
rd_lvl[7]	13285	1		T205	507		T207	735		T208	11
rd_lvl[8]	16218	1		T31	1308		T227	1928		T207	733
rd_lvl[9]	7942	1		T31	707		T227	537		T207	1270
rd_lvl[10]	5397	1		T207	197		T211	679		T330	1
rd_lvl[11]	8192	1		T31	108		T331	670		T227	37
rd_lvl[12]	5060	1		T331	350		T207	2		T332	447
rd_lvl[13]	3539	1		T207	1		T211	83		T330	38
rd_lvl[14]	5741	1		T7	641		T207	93		T280	612
rd_lvl[15]	6372	1		T24	344		T7	256		T32	440