Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	321819	1		T1	1		T2	1		T3	1175
all_pins[1]	321819	1		T1	1		T2	1		T3	1175
all_pins[2]	321819	1		T1	1		T2	1		T3	1175
all_pins[3]	321819	1		T1	1		T2	1		T3	1175
all_pins[4]	321819	1		T1	1		T2	1		T3	1175
all_pins[5]	321819	1		T1	1		T2	1		T3	1175

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1610778	1		T1	6		T2	6		T3	5876
values[0x1]	320136	1		T3	1174		T8	6022		T24	2624
transitions[0x0=>0x1]	288053	1		T3	1174		T8	5235		T24	1962
transitions[0x1=>0x0]	288047	1		T3	1174		T8	5235		T24	1962

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	321673	1		T1	1		T2	1		T3	1175
all_pins[0]	values[0x1]	146	1		T265	3		T266	4		T267	1
all_pins[0]	transitions[0x0=>0x1]	69	1		T265	1		T266	1		T321	3
all_pins[0]	transitions[0x1=>0x0]	96	1		T266	1		T267	3		T321	1
all_pins[1]	values[0x0]	321646	1		T1	1		T2	1		T3	1175
all_pins[1]	values[0x1]	173	1		T265	2		T266	4		T267	4
all_pins[1]	transitions[0x0=>0x1]	139	1		T265	2		T266	4		T267	3
all_pins[1]	transitions[0x1=>0x0]	3113	1		T24	331		T32	396		T353	480
all_pins[2]	values[0x0]	318672	1		T1	1		T2	1		T3	1175
all_pins[2]	values[0x1]	3147	1		T24	331		T32	396		T353	480
all_pins[2]	transitions[0x0=>0x1]	46	1		T323	1		T322	1		T324	1
all_pins[2]	transitions[0x1=>0x0]	209495	1		T8	4961		T24	651		T7	897
all_pins[3]	values[0x0]	109223	1		T1	1		T2	1		T3	1175
all_pins[3]	values[0x1]	212596	1		T8	4961		T24	982		T7	897
all_pins[3]	transitions[0x0=>0x1]	183792	1		T8	4174		T24	651		T7	897
all_pins[3]	transitions[0x1=>0x0]	75194	1		T3	1174		T8	274		T24	980
all_pins[4]	values[0x0]	217821	1		T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	103998	1		T3	1174		T8	1061		T24	1311
all_pins[4]	transitions[0x0=>0x1]	103978	1		T3	1174		T8	1061		T24	1311
all_pins[4]	transitions[0x1=>0x0]	56	1		T265	1		T267	1		T321	1
all_pins[5]	values[0x0]	321743	1		T1	1		T2	1		T3	1175
all_pins[5]	values[0x1]	76	1		T265	3		T267	1		T321	2
all_pins[5]	transitions[0x0=>0x1]	29	1		T265	2		T321	1		T322	1
all_pins[5]	transitions[0x1=>0x0]	93	1		T265	2		T266	3		T267	1