Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	281	1		T265	7		T266	4		T267	4
all_values[1]	281	1		T265	7		T266	4		T267	4
all_values[2]	281	1		T265	7		T266	4		T267	4
all_values[3]	281	1		T265	7		T266	4		T267	4
all_values[4]	281	1		T265	7		T266	4		T267	4
all_values[5]	281	1		T265	7		T266	4		T267	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	928	1		T265	26		T266	14		T267	13
auto[1]	758	1		T265	16		T266	10		T267	11

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	539	1		T265	12		T266	8		T267	7
auto[1]	1147	1		T265	30		T266	16		T267	17

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	992	1		T265	21		T266	15		T267	14
auto[1]	694	1		T265	21		T266	9		T267	10

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	93	1		T265	3		T267	2		T320	2
all_values[0]	auto[0]	auto[1]	auto[1]	62	1		T265	1		T266	3		T321	1
all_values[0]	auto[1]	auto[0]	auto[1]	61	1		T265	2		T267	1		T321	1
all_values[0]	auto[1]	auto[1]	auto[1]	65	1		T265	1		T266	1		T267	1
all_values[1]	auto[0]	auto[0]	auto[1]	78	1		T265	2		T266	1		T267	1
all_values[1]	auto[0]	auto[1]	auto[1]	98	1		T266	1		T267	3		T321	1
all_values[1]	auto[1]	auto[0]	auto[1]	65	1		T265	5		T266	1		T321	2
all_values[1]	auto[1]	auto[1]	auto[1]	40	1		T266	1		T320	1		T322	1
all_values[2]	auto[0]	auto[0]	auto[0]	84	1		T265	3		T266	3		T267	1
all_values[2]	auto[0]	auto[1]	auto[0]	80	1		T265	2		T267	1		T321	2
all_values[2]	auto[1]	auto[0]	auto[1]	64	1		T265	2		T266	1		T267	2
all_values[2]	auto[1]	auto[1]	auto[1]	53	1		T323	1		T322	1		T324	2
all_values[3]	auto[0]	auto[0]	auto[0]	104	1		T265	1		T266	2		T321	2
all_values[3]	auto[0]	auto[1]	auto[0]	64	1		T265	1		T266	2		T267	2
all_values[3]	auto[1]	auto[0]	auto[1]	67	1		T265	4		T267	2		T321	1
all_values[3]	auto[1]	auto[1]	auto[1]	46	1		T265	1		T321	1		T323	1
all_values[4]	auto[0]	auto[0]	auto[0]	63	1		T265	1		T321	1		T320	1
all_values[4]	auto[0]	auto[0]	auto[1]	30	1		T266	1		T320	2		T325	1
all_values[4]	auto[0]	auto[1]	auto[0]	44	1		T267	2		T321	2		T323	2
all_values[4]	auto[0]	auto[1]	auto[1]	29	1		T265	2		T266	1		T322	1
all_values[4]	auto[1]	auto[0]	auto[1]	63	1		T266	1		T267	1		T322	1
all_values[4]	auto[1]	auto[1]	auto[1]	52	1		T265	4		T266	1		T267	1
all_values[5]	auto[0]	auto[0]	auto[0]	64	1		T265	3		T266	1		T267	1
all_values[5]	auto[0]	auto[0]	auto[1]	21	1		T321	1		T322	1		T326	1
all_values[5]	auto[0]	auto[1]	auto[0]	36	1		T265	1		T320	1		T322	1
all_values[5]	auto[0]	auto[1]	auto[1]	42	1		T265	1		T267	1		T324	1
all_values[5]	auto[1]	auto[0]	auto[1]	71	1		T266	3		T267	2		T321	2
all_values[5]	auto[1]	auto[1]	auto[1]	47	1		T265	2		T321	1		T322	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal