| T1082 |
/workspace/coverage/default/3.flash_ctrl_wo.1869364741 |
|
|
Apr 21 02:08:10 PM PDT 24 |
Apr 21 02:10:42 PM PDT 24 |
3974049400 ps |
| T1083 |
/workspace/coverage/default/44.flash_ctrl_hw_sec_otp.633973625 |
|
|
Apr 21 02:14:36 PM PDT 24 |
Apr 21 02:15:38 PM PDT 24 |
1949235500 ps |
| T1084 |
/workspace/coverage/default/1.flash_ctrl_re_evict.1515775286 |
|
|
Apr 21 02:08:00 PM PDT 24 |
Apr 21 02:08:37 PM PDT 24 |
100403100 ps |
| T1085 |
/workspace/coverage/default/28.flash_ctrl_connect.276124503 |
|
|
Apr 21 02:13:15 PM PDT 24 |
Apr 21 02:13:31 PM PDT 24 |
14786600 ps |
| T1086 |
/workspace/coverage/default/6.flash_ctrl_connect.246241533 |
|
|
Apr 21 02:09:12 PM PDT 24 |
Apr 21 02:09:28 PM PDT 24 |
16314300 ps |
| T1087 |
/workspace/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.2083581152 |
|
|
Apr 21 02:11:34 PM PDT 24 |
Apr 21 02:16:35 PM PDT 24 |
10012913700 ps |
| T1088 |
/workspace/coverage/default/0.flash_ctrl_config_regwen.2430880308 |
|
|
Apr 21 02:08:02 PM PDT 24 |
Apr 21 02:08:16 PM PDT 24 |
77722900 ps |
| T1089 |
/workspace/coverage/default/15.flash_ctrl_re_evict.1376754675 |
|
|
Apr 21 02:11:19 PM PDT 24 |
Apr 21 02:11:55 PM PDT 24 |
411050400 ps |
| T1090 |
/workspace/coverage/default/37.flash_ctrl_alert_test.3554612045 |
|
|
Apr 21 02:14:08 PM PDT 24 |
Apr 21 02:14:22 PM PDT 24 |
28784900 ps |
| T1091 |
/workspace/coverage/default/47.flash_ctrl_otp_reset.2307930612 |
|
|
Apr 21 02:14:41 PM PDT 24 |
Apr 21 02:16:54 PM PDT 24 |
39205000 ps |
| T1092 |
/workspace/coverage/default/17.flash_ctrl_rw_evict.4093942187 |
|
|
Apr 21 02:11:42 PM PDT 24 |
Apr 21 02:12:14 PM PDT 24 |
245630300 ps |
| T1093 |
/workspace/coverage/default/0.flash_ctrl_error_mp.3508702895 |
|
|
Apr 21 02:07:58 PM PDT 24 |
Apr 21 02:43:47 PM PDT 24 |
8382843100 ps |
| T1094 |
/workspace/coverage/default/22.flash_ctrl_hw_sec_otp.2759629394 |
|
|
Apr 21 02:12:25 PM PDT 24 |
Apr 21 02:13:28 PM PDT 24 |
3638573100 ps |
| T1095 |
/workspace/coverage/default/14.flash_ctrl_ro.2180476272 |
|
|
Apr 21 02:11:08 PM PDT 24 |
Apr 21 02:12:37 PM PDT 24 |
1779956900 ps |
| T1096 |
/workspace/coverage/default/3.flash_ctrl_stress_all.3511709446 |
|
|
Apr 21 02:08:19 PM PDT 24 |
Apr 21 02:10:15 PM PDT 24 |
44566700 ps |
| T1097 |
/workspace/coverage/default/6.flash_ctrl_rw_serr.4204785897 |
|
|
Apr 21 02:09:08 PM PDT 24 |
Apr 21 02:18:42 PM PDT 24 |
19682785000 ps |
| T1098 |
/workspace/coverage/default/1.flash_ctrl_serr_counter.1757214972 |
|
|
Apr 21 02:07:52 PM PDT 24 |
Apr 21 02:09:15 PM PDT 24 |
1540068900 ps |
| T1099 |
/workspace/coverage/default/9.flash_ctrl_fetch_code.3823867830 |
|
|
Apr 21 02:09:55 PM PDT 24 |
Apr 21 02:10:22 PM PDT 24 |
475170100 ps |
| T1100 |
/workspace/coverage/default/42.flash_ctrl_smoke.434132869 |
|
|
Apr 21 02:14:24 PM PDT 24 |
Apr 21 02:16:05 PM PDT 24 |
53043700 ps |
| T1101 |
/workspace/coverage/default/30.flash_ctrl_connect.3002277958 |
|
|
Apr 21 02:13:28 PM PDT 24 |
Apr 21 02:13:44 PM PDT 24 |
13184300 ps |
| T251 |
/workspace/coverage/default/1.flash_ctrl_integrity.4136038067 |
|
|
Apr 21 02:08:01 PM PDT 24 |
Apr 21 02:16:25 PM PDT 24 |
2626204100 ps |
| T1102 |
/workspace/coverage/default/17.flash_ctrl_rw.1924651935 |
|
|
Apr 21 02:11:40 PM PDT 24 |
Apr 21 02:19:34 PM PDT 24 |
12583177400 ps |
| T1103 |
/workspace/coverage/default/7.flash_ctrl_rw_serr.1496677405 |
|
|
Apr 21 02:09:23 PM PDT 24 |
Apr 21 02:18:24 PM PDT 24 |
13195399900 ps |
| T1104 |
/workspace/coverage/default/30.flash_ctrl_smoke.4188016672 |
|
|
Apr 21 02:13:20 PM PDT 24 |
Apr 21 02:14:36 PM PDT 24 |
38608400 ps |
| T1105 |
/workspace/coverage/default/7.flash_ctrl_wo.1459330373 |
|
|
Apr 21 02:09:26 PM PDT 24 |
Apr 21 02:11:25 PM PDT 24 |
2768094800 ps |
| T1106 |
/workspace/coverage/default/54.flash_ctrl_connect.1898083768 |
|
|
Apr 21 02:14:58 PM PDT 24 |
Apr 21 02:15:14 PM PDT 24 |
46193200 ps |
| T142 |
/workspace/coverage/default/1.flash_ctrl_mid_op_rst.3967641964 |
|
|
Apr 21 02:08:00 PM PDT 24 |
Apr 21 02:09:18 PM PDT 24 |
6357560000 ps |
| T1107 |
/workspace/coverage/default/3.flash_ctrl_ro_derr.2073741913 |
|
|
Apr 21 02:08:15 PM PDT 24 |
Apr 21 02:10:02 PM PDT 24 |
720956300 ps |
| T1108 |
/workspace/coverage/default/3.flash_ctrl_rw_evict_all_en.942088964 |
|
|
Apr 21 02:08:26 PM PDT 24 |
Apr 21 02:08:58 PM PDT 24 |
50014000 ps |
| T1109 |
/workspace/coverage/default/16.flash_ctrl_prog_reset.2270064600 |
|
|
Apr 21 02:11:29 PM PDT 24 |
Apr 21 02:11:43 PM PDT 24 |
26904500 ps |
| T1110 |
/workspace/coverage/default/6.flash_ctrl_mp_regions.1909772728 |
|
|
Apr 21 02:09:01 PM PDT 24 |
Apr 21 02:10:58 PM PDT 24 |
3129237100 ps |
| T1111 |
/workspace/coverage/default/31.flash_ctrl_hw_sec_otp.2137248644 |
|
|
Apr 21 02:13:27 PM PDT 24 |
Apr 21 02:14:27 PM PDT 24 |
6446005900 ps |
| T1112 |
/workspace/coverage/default/10.flash_ctrl_wo.726517997 |
|
|
Apr 21 02:10:12 PM PDT 24 |
Apr 21 02:12:55 PM PDT 24 |
9649075000 ps |
| T1113 |
/workspace/coverage/default/8.flash_ctrl_error_mp.3888970501 |
|
|
Apr 21 02:09:47 PM PDT 24 |
Apr 21 02:51:55 PM PDT 24 |
23626136800 ps |
| T1114 |
/workspace/coverage/default/26.flash_ctrl_intr_rd_slow_flash.2364589870 |
|
|
Apr 21 02:13:00 PM PDT 24 |
Apr 21 02:16:39 PM PDT 24 |
7914050200 ps |
| T393 |
/workspace/coverage/default/33.flash_ctrl_sec_info_access.2935290907 |
|
|
Apr 21 02:13:42 PM PDT 24 |
Apr 21 02:14:45 PM PDT 24 |
571389700 ps |
| T1115 |
/workspace/coverage/default/10.flash_ctrl_alert_test.959849681 |
|
|
Apr 21 02:10:23 PM PDT 24 |
Apr 21 02:10:37 PM PDT 24 |
108262400 ps |
| T1116 |
/workspace/coverage/default/66.flash_ctrl_otp_reset.1923855347 |
|
|
Apr 21 02:15:07 PM PDT 24 |
Apr 21 02:17:19 PM PDT 24 |
145031000 ps |
| T1117 |
/workspace/coverage/default/2.flash_ctrl_stress_all.493484096 |
|
|
Apr 21 02:08:11 PM PDT 24 |
Apr 21 02:13:44 PM PDT 24 |
65811300 ps |
| T1118 |
/workspace/coverage/default/26.flash_ctrl_disable.1011842670 |
|
|
Apr 21 02:13:01 PM PDT 24 |
Apr 21 02:13:22 PM PDT 24 |
46382800 ps |
| T1119 |
/workspace/coverage/default/24.flash_ctrl_rw_evict.3197286936 |
|
|
Apr 21 02:12:45 PM PDT 24 |
Apr 21 02:13:14 PM PDT 24 |
65835700 ps |
| T151 |
/workspace/coverage/default/22.flash_ctrl_prog_reset.2000201363 |
|
|
Apr 21 02:12:31 PM PDT 24 |
Apr 21 02:12:46 PM PDT 24 |
61028500 ps |
| T1120 |
/workspace/coverage/default/0.flash_ctrl_mp_regions.3450605877 |
|
|
Apr 21 02:07:46 PM PDT 24 |
Apr 21 02:16:59 PM PDT 24 |
14700109900 ps |
| T1121 |
/workspace/coverage/default/2.flash_ctrl_otp_reset.207806148 |
|
|
Apr 21 02:07:59 PM PDT 24 |
Apr 21 02:10:14 PM PDT 24 |
134633600 ps |
| T1122 |
/workspace/coverage/default/26.flash_ctrl_smoke.994887292 |
|
|
Apr 21 02:12:58 PM PDT 24 |
Apr 21 02:14:13 PM PDT 24 |
71508200 ps |
| T1123 |
/workspace/coverage/default/42.flash_ctrl_otp_reset.2399822725 |
|
|
Apr 21 02:14:24 PM PDT 24 |
Apr 21 02:16:36 PM PDT 24 |
67894000 ps |
| T291 |
/workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.3836124050 |
|
|
Apr 21 02:11:49 PM PDT 24 |
Apr 21 02:12:42 PM PDT 24 |
10038540100 ps |
| T1124 |
/workspace/coverage/default/61.flash_ctrl_otp_reset.2312131074 |
|
|
Apr 21 02:15:02 PM PDT 24 |
Apr 21 02:16:54 PM PDT 24 |
515855200 ps |
| T1125 |
/workspace/coverage/default/2.flash_ctrl_re_evict.3735424718 |
|
|
Apr 21 02:08:01 PM PDT 24 |
Apr 21 02:08:38 PM PDT 24 |
104020100 ps |
| T1126 |
/workspace/coverage/default/5.flash_ctrl_intr_wr.334457180 |
|
|
Apr 21 02:08:55 PM PDT 24 |
Apr 21 02:10:30 PM PDT 24 |
4038907900 ps |
| T1127 |
/workspace/coverage/default/12.flash_ctrl_ro.2934195058 |
|
|
Apr 21 02:10:38 PM PDT 24 |
Apr 21 02:12:09 PM PDT 24 |
467969300 ps |
| T1128 |
/workspace/coverage/default/17.flash_ctrl_invalid_op.3003665284 |
|
|
Apr 21 02:11:34 PM PDT 24 |
Apr 21 02:12:37 PM PDT 24 |
1685215300 ps |
| T1129 |
/workspace/coverage/default/60.flash_ctrl_connect.2852175195 |
|
|
Apr 21 02:15:02 PM PDT 24 |
Apr 21 02:15:18 PM PDT 24 |
17062600 ps |
| T1130 |
/workspace/coverage/default/21.flash_ctrl_rw_evict.1096319869 |
|
|
Apr 21 02:12:27 PM PDT 24 |
Apr 21 02:12:56 PM PDT 24 |
119325900 ps |
| T152 |
/workspace/coverage/default/3.flash_ctrl_mid_op_rst.4267498558 |
|
|
Apr 21 02:08:13 PM PDT 24 |
Apr 21 02:09:26 PM PDT 24 |
1988768100 ps |
| T395 |
/workspace/coverage/default/43.flash_ctrl_sec_info_access.1797958281 |
|
|
Apr 21 02:14:38 PM PDT 24 |
Apr 21 02:15:44 PM PDT 24 |
6626727000 ps |
| T1131 |
/workspace/coverage/default/47.flash_ctrl_connect.3919288526 |
|
|
Apr 21 02:14:44 PM PDT 24 |
Apr 21 02:15:00 PM PDT 24 |
25309200 ps |
| T1132 |
/workspace/coverage/default/49.flash_ctrl_smoke.2236195566 |
|
|
Apr 21 02:14:49 PM PDT 24 |
Apr 21 02:15:39 PM PDT 24 |
60670100 ps |
| T410 |
/workspace/coverage/default/30.flash_ctrl_sec_info_access.736260001 |
|
|
Apr 21 02:13:27 PM PDT 24 |
Apr 21 02:14:34 PM PDT 24 |
3615516700 ps |
| T1133 |
/workspace/coverage/default/44.flash_ctrl_alert_test.3721134560 |
|
|
Apr 21 02:14:40 PM PDT 24 |
Apr 21 02:14:53 PM PDT 24 |
270566200 ps |
| T1134 |
/workspace/coverage/default/8.flash_ctrl_rw_derr.919219098 |
|
|
Apr 21 02:09:49 PM PDT 24 |
Apr 21 02:19:21 PM PDT 24 |
3849137900 ps |
| T1135 |
/workspace/coverage/default/5.flash_ctrl_ro.2373154567 |
|
|
Apr 21 02:08:55 PM PDT 24 |
Apr 21 02:10:39 PM PDT 24 |
455880300 ps |
| T265 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.664557616 |
|
|
Apr 21 12:40:17 PM PDT 24 |
Apr 21 12:40:30 PM PDT 24 |
16629200 ps |
| T266 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.2621250229 |
|
|
Apr 21 12:40:24 PM PDT 24 |
Apr 21 12:40:38 PM PDT 24 |
26694500 ps |
| T267 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.238997246 |
|
|
Apr 21 12:40:17 PM PDT 24 |
Apr 21 12:40:30 PM PDT 24 |
221213300 ps |
| T68 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.726122581 |
|
|
Apr 21 12:40:13 PM PDT 24 |
Apr 21 12:40:28 PM PDT 24 |
136413100 ps |
| T69 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.844043046 |
|
|
Apr 21 12:40:08 PM PDT 24 |
Apr 21 12:40:43 PM PDT 24 |
889113800 ps |
| T321 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.1133377587 |
|
|
Apr 21 12:39:53 PM PDT 24 |
Apr 21 12:40:07 PM PDT 24 |
75348600 ps |
| T70 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.911891668 |
|
|
Apr 21 12:40:15 PM PDT 24 |
Apr 21 12:40:31 PM PDT 24 |
547318700 ps |
| T320 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.1660344420 |
|
|
Apr 21 12:40:13 PM PDT 24 |
Apr 21 12:40:27 PM PDT 24 |
17303100 ps |
| T323 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.3986516564 |
|
|
Apr 21 12:40:21 PM PDT 24 |
Apr 21 12:40:34 PM PDT 24 |
44984700 ps |
| T197 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.4045685201 |
|
|
Apr 21 12:39:50 PM PDT 24 |
Apr 21 12:40:09 PM PDT 24 |
58182500 ps |
| T236 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2968193936 |
|
|
Apr 21 12:39:43 PM PDT 24 |
Apr 21 12:39:57 PM PDT 24 |
62460100 ps |
| T198 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.2848078938 |
|
|
Apr 21 12:40:24 PM PDT 24 |
Apr 21 12:40:44 PM PDT 24 |
376474000 ps |
| T252 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.3098184850 |
|
|
Apr 21 12:40:13 PM PDT 24 |
Apr 21 12:40:31 PM PDT 24 |
75265800 ps |
| T200 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.1603965994 |
|
|
Apr 21 12:40:07 PM PDT 24 |
Apr 21 12:40:27 PM PDT 24 |
274417700 ps |
| T237 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.990151096 |
|
|
Apr 21 12:39:48 PM PDT 24 |
Apr 21 12:40:03 PM PDT 24 |
55465500 ps |
| T199 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.2374039117 |
|
|
Apr 21 12:39:57 PM PDT 24 |
Apr 21 12:46:19 PM PDT 24 |
1439137500 ps |
| T258 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1167187370 |
|
|
Apr 21 12:40:02 PM PDT 24 |
Apr 21 12:40:20 PM PDT 24 |
36306300 ps |
| T1136 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.3789405538 |
|
|
Apr 21 12:40:15 PM PDT 24 |
Apr 21 12:40:28 PM PDT 24 |
35226000 ps |
| T259 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1317202660 |
|
|
Apr 21 12:40:02 PM PDT 24 |
Apr 21 12:40:19 PM PDT 24 |
122492400 ps |
| T219 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.1615297801 |
|
|
Apr 21 12:40:12 PM PDT 24 |
Apr 21 12:40:30 PM PDT 24 |
80393400 ps |
| T261 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2966876540 |
|
|
Apr 21 12:40:13 PM PDT 24 |
Apr 21 12:40:32 PM PDT 24 |
376420900 ps |
| T221 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.3515440523 |
|
|
Apr 21 12:40:06 PM PDT 24 |
Apr 21 12:40:22 PM PDT 24 |
390085700 ps |
| T1137 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.3187270409 |
|
|
Apr 21 12:40:18 PM PDT 24 |
Apr 21 12:40:34 PM PDT 24 |
41884700 ps |
| T262 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.3308806909 |
|
|
Apr 21 12:40:06 PM PDT 24 |
Apr 21 12:40:24 PM PDT 24 |
71267800 ps |
| T1138 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.1751466190 |
|
|
Apr 21 12:39:59 PM PDT 24 |
Apr 21 12:40:29 PM PDT 24 |
152759100 ps |
| T238 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1187289500 |
|
|
Apr 21 12:39:55 PM PDT 24 |
Apr 21 12:40:09 PM PDT 24 |
28598300 ps |
| T322 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.2188341551 |
|
|
Apr 21 12:40:14 PM PDT 24 |
Apr 21 12:40:28 PM PDT 24 |
64843000 ps |
| T324 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.221523989 |
|
|
Apr 21 12:40:20 PM PDT 24 |
Apr 21 12:40:35 PM PDT 24 |
30554300 ps |
| T1139 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.5653503 |
|
|
Apr 21 12:40:07 PM PDT 24 |
Apr 21 12:40:21 PM PDT 24 |
55878800 ps |
| T260 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.204172205 |
|
|
Apr 21 12:40:13 PM PDT 24 |
Apr 21 12:40:27 PM PDT 24 |
34106100 ps |
| T1140 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2219328816 |
|
|
Apr 21 12:40:11 PM PDT 24 |
Apr 21 12:40:27 PM PDT 24 |
22917300 ps |
| T1141 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.3953106232 |
|
|
Apr 21 12:40:13 PM PDT 24 |
Apr 21 12:40:29 PM PDT 24 |
24525400 ps |
| T1142 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.300028075 |
|
|
Apr 21 12:39:56 PM PDT 24 |
Apr 21 12:40:10 PM PDT 24 |
21334100 ps |
| T220 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.1701010048 |
|
|
Apr 21 12:40:22 PM PDT 24 |
Apr 21 12:40:39 PM PDT 24 |
82801300 ps |
| T239 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.4153050792 |
|
|
Apr 21 12:39:57 PM PDT 24 |
Apr 21 12:40:11 PM PDT 24 |
46044100 ps |
| T1143 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.1014327370 |
|
|
Apr 21 12:39:53 PM PDT 24 |
Apr 21 12:40:07 PM PDT 24 |
43374500 ps |
| T240 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.3181785645 |
|
|
Apr 21 12:40:04 PM PDT 24 |
Apr 21 12:40:18 PM PDT 24 |
36488900 ps |
| T231 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.3801808417 |
|
|
Apr 21 12:40:14 PM PDT 24 |
Apr 21 12:40:32 PM PDT 24 |
176506300 ps |
| T296 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2476525947 |
|
|
Apr 21 12:39:53 PM PDT 24 |
Apr 21 12:40:14 PM PDT 24 |
847514100 ps |
| T326 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.367068008 |
|
|
Apr 21 12:40:13 PM PDT 24 |
Apr 21 12:40:27 PM PDT 24 |
17647800 ps |
| T297 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2921502514 |
|
|
Apr 21 12:40:24 PM PDT 24 |
Apr 21 12:40:59 PM PDT 24 |
356443100 ps |
| T365 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.2957679282 |
|
|
Apr 21 12:40:21 PM PDT 24 |
Apr 21 12:40:36 PM PDT 24 |
306400900 ps |
| T298 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.567276326 |
|
|
Apr 21 12:40:02 PM PDT 24 |
Apr 21 12:40:21 PM PDT 24 |
240777500 ps |
| T1144 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.1835229879 |
|
|
Apr 21 12:39:54 PM PDT 24 |
Apr 21 12:40:10 PM PDT 24 |
39107500 ps |
| T1145 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.4281658349 |
|
|
Apr 21 12:40:08 PM PDT 24 |
Apr 21 12:40:24 PM PDT 24 |
127485700 ps |
| T1146 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.4068947027 |
|
|
Apr 21 12:40:16 PM PDT 24 |
Apr 21 12:40:30 PM PDT 24 |
13777700 ps |
| T1147 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.3097462980 |
|
|
Apr 21 12:40:21 PM PDT 24 |
Apr 21 12:40:35 PM PDT 24 |
22839300 ps |
| T232 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.387581950 |
|
|
Apr 21 12:40:15 PM PDT 24 |
Apr 21 12:40:34 PM PDT 24 |
58526500 ps |
| T1148 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.1476748346 |
|
|
Apr 21 12:40:09 PM PDT 24 |
Apr 21 12:40:25 PM PDT 24 |
40832400 ps |
| T419 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.107400570 |
|
|
Apr 21 12:39:47 PM PDT 24 |
Apr 21 12:40:21 PM PDT 24 |
464352500 ps |
| T233 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.281585362 |
|
|
Apr 21 12:40:06 PM PDT 24 |
Apr 21 12:46:28 PM PDT 24 |
834013900 ps |
| T325 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.1972247986 |
|
|
Apr 21 12:40:14 PM PDT 24 |
Apr 21 12:40:28 PM PDT 24 |
60476700 ps |
| T234 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.207566277 |
|
|
Apr 21 12:39:47 PM PDT 24 |
Apr 21 12:40:05 PM PDT 24 |
130967300 ps |
| T235 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.2416750167 |
|
|
Apr 21 12:40:03 PM PDT 24 |
Apr 21 12:40:20 PM PDT 24 |
72637900 ps |
| T1149 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.2939650263 |
|
|
Apr 21 12:40:24 PM PDT 24 |
Apr 21 12:40:41 PM PDT 24 |
171221800 ps |
| T1150 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.1075664257 |
|
|
Apr 21 12:40:07 PM PDT 24 |
Apr 21 12:40:25 PM PDT 24 |
62675400 ps |
| T1151 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.2387163074 |
|
|
Apr 21 12:39:59 PM PDT 24 |
Apr 21 12:40:15 PM PDT 24 |
21299300 ps |
| T299 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1227306572 |
|
|
Apr 21 12:40:16 PM PDT 24 |
Apr 21 12:40:34 PM PDT 24 |
60134200 ps |
| T354 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1905862997 |
|
|
Apr 21 12:40:03 PM PDT 24 |
Apr 21 12:40:21 PM PDT 24 |
52686300 ps |
| T255 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1958440903 |
|
|
Apr 21 12:40:04 PM PDT 24 |
Apr 21 12:54:52 PM PDT 24 |
804084500 ps |
| T1152 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.632838429 |
|
|
Apr 21 12:40:21 PM PDT 24 |
Apr 21 12:40:35 PM PDT 24 |
134727200 ps |
| T1153 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.1667387366 |
|
|
Apr 21 12:39:59 PM PDT 24 |
Apr 21 12:40:13 PM PDT 24 |
45199400 ps |
| T1154 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.544503596 |
|
|
Apr 21 12:39:55 PM PDT 24 |
Apr 21 12:40:11 PM PDT 24 |
25242400 ps |
| T300 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2699698678 |
|
|
Apr 21 12:40:02 PM PDT 24 |
Apr 21 12:47:45 PM PDT 24 |
1796177500 ps |
| T264 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.3687320071 |
|
|
Apr 21 12:40:18 PM PDT 24 |
Apr 21 12:40:37 PM PDT 24 |
107919200 ps |
| T1155 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.851984092 |
|
|
Apr 21 12:40:12 PM PDT 24 |
Apr 21 12:40:26 PM PDT 24 |
51511800 ps |
| T301 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.619082465 |
|
|
Apr 21 12:39:56 PM PDT 24 |
Apr 21 12:40:43 PM PDT 24 |
309028400 ps |
| T1156 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.146240469 |
|
|
Apr 21 12:39:58 PM PDT 24 |
Apr 21 12:41:20 PM PDT 24 |
4457957800 ps |
| T1157 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.3409628557 |
|
|
Apr 21 12:40:03 PM PDT 24 |
Apr 21 12:40:19 PM PDT 24 |
29165600 ps |
| T1158 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2440814163 |
|
|
Apr 21 12:40:01 PM PDT 24 |
Apr 21 12:40:15 PM PDT 24 |
49477800 ps |
| T302 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.333739053 |
|
|
Apr 21 12:40:04 PM PDT 24 |
Apr 21 12:40:50 PM PDT 24 |
90266100 ps |
| T1159 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.506690023 |
|
|
Apr 21 12:40:12 PM PDT 24 |
Apr 21 12:40:29 PM PDT 24 |
58322600 ps |
| T1160 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1150037833 |
|
|
Apr 21 12:40:22 PM PDT 24 |
Apr 21 12:40:51 PM PDT 24 |
70563300 ps |
| T1161 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.1387221932 |
|
|
Apr 21 12:40:20 PM PDT 24 |
Apr 21 12:40:34 PM PDT 24 |
15429200 ps |
| T268 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3086116232 |
|
|
Apr 21 12:40:04 PM PDT 24 |
Apr 21 12:40:24 PM PDT 24 |
120001300 ps |
| T303 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.3345004430 |
|
|
Apr 21 12:39:46 PM PDT 24 |
Apr 21 12:40:08 PM PDT 24 |
211812800 ps |
| T1162 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1196634865 |
|
|
Apr 21 12:39:56 PM PDT 24 |
Apr 21 12:40:27 PM PDT 24 |
18900300 ps |
| T1163 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3207081377 |
|
|
Apr 21 12:40:22 PM PDT 24 |
Apr 21 12:40:40 PM PDT 24 |
32838900 ps |
| T1164 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.1216071872 |
|
|
Apr 21 12:40:13 PM PDT 24 |
Apr 21 12:40:26 PM PDT 24 |
22581100 ps |
| T355 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3204343697 |
|
|
Apr 21 12:40:16 PM PDT 24 |
Apr 21 12:52:54 PM PDT 24 |
682558400 ps |
| T263 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.3726039233 |
|
|
Apr 21 12:40:19 PM PDT 24 |
Apr 21 12:40:35 PM PDT 24 |
33442700 ps |
| T270 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.653373914 |
|
|
Apr 21 12:40:11 PM PDT 24 |
Apr 21 12:40:30 PM PDT 24 |
222467400 ps |
| T1165 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.2996787642 |
|
|
Apr 21 12:40:01 PM PDT 24 |
Apr 21 12:40:30 PM PDT 24 |
105587900 ps |
| T1166 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.2626263023 |
|
|
Apr 21 12:40:25 PM PDT 24 |
Apr 21 12:40:39 PM PDT 24 |
30489400 ps |
| T273 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.187031210 |
|
|
Apr 21 12:39:57 PM PDT 24 |
Apr 21 12:40:14 PM PDT 24 |
38726700 ps |
| T276 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2221065861 |
|
|
Apr 21 12:40:13 PM PDT 24 |
Apr 21 12:52:45 PM PDT 24 |
1309920800 ps |
| T1167 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.3976584010 |
|
|
Apr 21 12:40:12 PM PDT 24 |
Apr 21 12:40:26 PM PDT 24 |
107520600 ps |
| T1168 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.3846742800 |
|
|
Apr 21 12:40:06 PM PDT 24 |
Apr 21 12:40:20 PM PDT 24 |
20835000 ps |
| T1169 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.3524487061 |
|
|
Apr 21 12:40:34 PM PDT 24 |
Apr 21 12:40:48 PM PDT 24 |
51195800 ps |
| T1170 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.2888398490 |
|
|
Apr 21 12:40:15 PM PDT 24 |
Apr 21 12:40:34 PM PDT 24 |
270712400 ps |
| T1171 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3007278974 |
|
|
Apr 21 12:40:22 PM PDT 24 |
Apr 21 12:40:37 PM PDT 24 |
101988800 ps |
| T1172 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.692070958 |
|
|
Apr 21 12:39:53 PM PDT 24 |
Apr 21 12:40:06 PM PDT 24 |
56792300 ps |
| T274 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.1509834640 |
|
|
Apr 21 12:40:05 PM PDT 24 |
Apr 21 12:52:41 PM PDT 24 |
849670100 ps |
| T1173 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.1549838125 |
|
|
Apr 21 12:40:08 PM PDT 24 |
Apr 21 12:40:22 PM PDT 24 |
54759600 ps |
| T275 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1762283310 |
|
|
Apr 21 12:40:12 PM PDT 24 |
Apr 21 12:40:28 PM PDT 24 |
61929100 ps |
| T1174 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.301708449 |
|
|
Apr 21 12:40:10 PM PDT 24 |
Apr 21 12:40:24 PM PDT 24 |
16909700 ps |
| T1175 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1325047391 |
|
|
Apr 21 12:40:22 PM PDT 24 |
Apr 21 12:41:40 PM PDT 24 |
12871839200 ps |
| T1176 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.3428459855 |
|
|
Apr 21 12:40:01 PM PDT 24 |
Apr 21 12:40:17 PM PDT 24 |
14665000 ps |
| T357 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.3314445091 |
|
|
Apr 21 12:40:07 PM PDT 24 |
Apr 21 12:54:59 PM PDT 24 |
358777500 ps |
| T1177 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.4172599849 |
|
|
Apr 21 12:40:14 PM PDT 24 |
Apr 21 12:40:32 PM PDT 24 |
44901000 ps |
| T1178 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.141351674 |
|
|
Apr 21 12:40:25 PM PDT 24 |
Apr 21 12:40:42 PM PDT 24 |
33385700 ps |
| T1179 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.2583354347 |
|
|
Apr 21 12:40:02 PM PDT 24 |
Apr 21 12:40:22 PM PDT 24 |
42191200 ps |
| T1180 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.2676141803 |
|
|
Apr 21 12:39:51 PM PDT 24 |
Apr 21 12:40:46 PM PDT 24 |
8469620700 ps |
| T1181 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.862024571 |
|
|
Apr 21 12:39:59 PM PDT 24 |
Apr 21 12:40:16 PM PDT 24 |
72236400 ps |
| T1182 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.2203292467 |
|
|
Apr 21 12:40:23 PM PDT 24 |
Apr 21 12:40:37 PM PDT 24 |
17158500 ps |
| T1183 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.248660099 |
|
|
Apr 21 12:40:39 PM PDT 24 |
Apr 21 12:40:53 PM PDT 24 |
15094800 ps |
| T1184 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.4194503212 |
|
|
Apr 21 12:40:18 PM PDT 24 |
Apr 21 12:40:32 PM PDT 24 |
56375800 ps |
| T1185 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3164969696 |
|
|
Apr 21 12:40:14 PM PDT 24 |
Apr 21 12:40:28 PM PDT 24 |
17133800 ps |
| T1186 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.3792145697 |
|
|
Apr 21 12:39:57 PM PDT 24 |
Apr 21 12:40:40 PM PDT 24 |
1189721500 ps |
| T1187 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.3784849355 |
|
|
Apr 21 12:40:27 PM PDT 24 |
Apr 21 12:40:41 PM PDT 24 |
58192400 ps |
| T1188 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.2972975205 |
|
|
Apr 21 12:39:54 PM PDT 24 |
Apr 21 12:40:11 PM PDT 24 |
52064000 ps |
| T1189 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.792731829 |
|
|
Apr 21 12:40:26 PM PDT 24 |
Apr 21 12:40:39 PM PDT 24 |
49872900 ps |
| T1190 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2662654198 |
|
|
Apr 21 12:40:11 PM PDT 24 |
Apr 21 12:40:25 PM PDT 24 |
46569200 ps |
| T1191 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.3944529547 |
|
|
Apr 21 12:40:30 PM PDT 24 |
Apr 21 12:40:44 PM PDT 24 |
24703200 ps |
| T1192 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.2029162354 |
|
|
Apr 21 12:40:12 PM PDT 24 |
Apr 21 12:40:26 PM PDT 24 |
25286100 ps |
| T1193 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.3268837667 |
|
|
Apr 21 12:40:12 PM PDT 24 |
Apr 21 12:40:26 PM PDT 24 |
22215200 ps |
| T1194 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1153791419 |
|
|
Apr 21 12:40:21 PM PDT 24 |
Apr 21 12:40:37 PM PDT 24 |
17156600 ps |
| T1195 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.2185652432 |
|
|
Apr 21 12:40:04 PM PDT 24 |
Apr 21 12:40:19 PM PDT 24 |
61134800 ps |
| T1196 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.2450204228 |
|
|
Apr 21 12:40:13 PM PDT 24 |
Apr 21 12:40:27 PM PDT 24 |
26537900 ps |
| T1197 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2402084964 |
|
|
Apr 21 12:39:54 PM PDT 24 |
Apr 21 12:40:11 PM PDT 24 |
135565400 ps |
| T277 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.4014088655 |
|
|
Apr 21 12:40:01 PM PDT 24 |
Apr 21 12:40:18 PM PDT 24 |
76488100 ps |
| T1198 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.875133120 |
|
|
Apr 21 12:40:11 PM PDT 24 |
Apr 21 12:40:28 PM PDT 24 |
80221900 ps |
| T362 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.301979919 |
|
|
Apr 21 12:40:28 PM PDT 24 |
Apr 21 12:48:05 PM PDT 24 |
268629200 ps |
| T271 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.122995102 |
|
|
Apr 21 12:40:23 PM PDT 24 |
Apr 21 12:40:42 PM PDT 24 |
197874700 ps |
| T1199 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.3173405497 |
|
|
Apr 21 12:40:12 PM PDT 24 |
Apr 21 12:40:26 PM PDT 24 |
43873900 ps |
| T1200 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.1047466073 |
|
|
Apr 21 12:40:23 PM PDT 24 |
Apr 21 12:40:37 PM PDT 24 |
29794700 ps |
| T1201 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.425347605 |
|
|
Apr 21 12:40:02 PM PDT 24 |
Apr 21 12:40:19 PM PDT 24 |
34225900 ps |
| T1202 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.973807101 |
|
|
Apr 21 12:40:02 PM PDT 24 |
Apr 21 12:47:39 PM PDT 24 |
2604640200 ps |
| T1203 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2951871449 |
|
|
Apr 21 12:40:11 PM PDT 24 |
Apr 21 12:40:29 PM PDT 24 |
130145500 ps |
| T1204 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.638140093 |
|
|
Apr 21 12:40:32 PM PDT 24 |
Apr 21 12:40:47 PM PDT 24 |
14582600 ps |
| T1205 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.1760469198 |
|
|
Apr 21 12:40:20 PM PDT 24 |
Apr 21 12:40:34 PM PDT 24 |
15841300 ps |
| T1206 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.1540967317 |
|
|
Apr 21 12:40:04 PM PDT 24 |
Apr 21 12:40:43 PM PDT 24 |
83943500 ps |
| T1207 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.139992051 |
|
|
Apr 21 12:40:17 PM PDT 24 |
Apr 21 12:40:31 PM PDT 24 |
12912900 ps |
| T1208 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.1284797025 |
|
|
Apr 21 12:40:00 PM PDT 24 |
Apr 21 12:40:18 PM PDT 24 |
573226600 ps |
| T356 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1665945163 |
|
|
Apr 21 12:40:09 PM PDT 24 |
Apr 21 12:47:48 PM PDT 24 |
1381516600 ps |
| T1209 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.145548013 |
|
|
Apr 21 12:40:15 PM PDT 24 |
Apr 21 12:40:28 PM PDT 24 |
22455200 ps |
| T1210 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.3367989807 |
|
|
Apr 21 12:40:17 PM PDT 24 |
Apr 21 12:40:31 PM PDT 24 |
31116600 ps |
| T1211 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.3906261955 |
|
|
Apr 21 12:40:07 PM PDT 24 |
Apr 21 12:40:21 PM PDT 24 |
45162200 ps |
| T1212 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1588703246 |
|
|
Apr 21 12:40:22 PM PDT 24 |
Apr 21 12:40:38 PM PDT 24 |
13083500 ps |
| T1213 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3032758367 |
|
|
Apr 21 12:39:52 PM PDT 24 |
Apr 21 12:40:08 PM PDT 24 |
23733800 ps |
| T304 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1838879158 |
|
|
Apr 21 12:40:17 PM PDT 24 |
Apr 21 12:40:37 PM PDT 24 |
423966500 ps |
| T1214 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.1989170504 |
|
|
Apr 21 12:40:01 PM PDT 24 |
Apr 21 12:41:16 PM PDT 24 |
3873869000 ps |
| T1215 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.1059155163 |
|
|
Apr 21 12:40:18 PM PDT 24 |
Apr 21 12:40:36 PM PDT 24 |
126020500 ps |
| T279 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.3312944773 |
|
|
Apr 21 12:39:58 PM PDT 24 |
Apr 21 12:47:30 PM PDT 24 |
600880800 ps |
| T278 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.3149640184 |
|
|
Apr 21 12:40:20 PM PDT 24 |
Apr 21 12:55:25 PM PDT 24 |
13304972800 ps |
| T1216 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.2396902390 |
|
|
Apr 21 12:39:41 PM PDT 24 |
Apr 21 12:40:00 PM PDT 24 |
82854200 ps |
| T360 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.75280399 |
|
|
Apr 21 12:40:03 PM PDT 24 |
Apr 21 12:47:39 PM PDT 24 |
441018300 ps |
| T272 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.3788710410 |
|
|
Apr 21 12:40:17 PM PDT 24 |
Apr 21 12:40:35 PM PDT 24 |
50012700 ps |
| T1217 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.3121541152 |
|
|
Apr 21 12:40:30 PM PDT 24 |
Apr 21 12:40:43 PM PDT 24 |
38660600 ps |
| T1218 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.445724810 |
|
|
Apr 21 12:39:59 PM PDT 24 |
Apr 21 12:40:15 PM PDT 24 |
167907100 ps |
| T1219 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.875502723 |
|
|
Apr 21 12:40:00 PM PDT 24 |
Apr 21 12:40:14 PM PDT 24 |
15510700 ps |
| T1220 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.2059451605 |
|
|
Apr 21 12:40:03 PM PDT 24 |
Apr 21 12:40:56 PM PDT 24 |
914704500 ps |
| T1221 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.934484831 |
|
|
Apr 21 12:39:54 PM PDT 24 |
Apr 21 12:40:09 PM PDT 24 |
15697000 ps |
| T1222 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3706277227 |
|
|
Apr 21 12:40:24 PM PDT 24 |
Apr 21 12:40:40 PM PDT 24 |
13455400 ps |
| T361 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.2480119259 |
|
|
Apr 21 12:39:55 PM PDT 24 |
Apr 21 12:52:26 PM PDT 24 |
668576200 ps |
| T1223 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.986272021 |
|
|
Apr 21 12:40:11 PM PDT 24 |
Apr 21 12:40:30 PM PDT 24 |
135452600 ps |
| T1224 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.551072191 |
|
|
Apr 21 12:40:15 PM PDT 24 |
Apr 21 12:40:54 PM PDT 24 |
1628860800 ps |
| T1225 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.618948394 |
|
|
Apr 21 12:40:12 PM PDT 24 |
Apr 21 12:40:30 PM PDT 24 |
217835300 ps |
| T1226 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.3460119707 |
|
|
Apr 21 12:40:11 PM PDT 24 |
Apr 21 12:40:25 PM PDT 24 |
42665900 ps |
| T1227 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.3615457337 |
|
|
Apr 21 12:40:22 PM PDT 24 |
Apr 21 12:40:36 PM PDT 24 |
18052100 ps |
| T1228 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.1291357265 |
|
|
Apr 21 12:40:13 PM PDT 24 |
Apr 21 12:40:27 PM PDT 24 |
48896400 ps |
| T269 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3065705400 |
|
|
Apr 21 12:40:20 PM PDT 24 |
Apr 21 12:40:36 PM PDT 24 |
63730500 ps |
| T1229 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.774145924 |
|
|
Apr 21 12:40:27 PM PDT 24 |
Apr 21 12:40:44 PM PDT 24 |
46014400 ps |
| T363 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.2203886569 |
|
|
Apr 21 12:40:42 PM PDT 24 |
Apr 21 12:55:30 PM PDT 24 |
366201100 ps |
| T1230 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.1854286324 |
|
|
Apr 21 12:39:46 PM PDT 24 |
Apr 21 12:40:06 PM PDT 24 |
104956400 ps |
| T1231 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.303092082 |
|
|
Apr 21 12:40:09 PM PDT 24 |
Apr 21 12:40:22 PM PDT 24 |
17718100 ps |
| T1232 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.3017994686 |
|
|
Apr 21 12:40:08 PM PDT 24 |
Apr 21 12:40:27 PM PDT 24 |
185932000 ps |
| T1233 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.3948893863 |
|
|
Apr 21 12:40:01 PM PDT 24 |
Apr 21 12:40:19 PM PDT 24 |
96659500 ps |
| T1234 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.2181466774 |
|
|
Apr 21 12:40:08 PM PDT 24 |
Apr 21 12:40:24 PM PDT 24 |
37747300 ps |
| T1235 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.1937645176 |
|
|
Apr 21 12:40:28 PM PDT 24 |
Apr 21 12:40:42 PM PDT 24 |
21807900 ps |
| T1236 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.4117125305 |
|
|
Apr 21 12:39:59 PM PDT 24 |
Apr 21 12:40:15 PM PDT 24 |
14330400 ps |
| T1237 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.4110460995 |
|
|
Apr 21 12:40:14 PM PDT 24 |
Apr 21 12:40:30 PM PDT 24 |
37327100 ps |
| T1238 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.2538682129 |
|
|
Apr 21 12:40:20 PM PDT 24 |
Apr 21 12:40:36 PM PDT 24 |
129259500 ps |
| T1239 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.1693945140 |
|
|
Apr 21 12:40:32 PM PDT 24 |
Apr 21 12:40:49 PM PDT 24 |
45611000 ps |
| T358 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.241810770 |
|
|
Apr 21 12:40:15 PM PDT 24 |
Apr 21 12:48:00 PM PDT 24 |
340442200 ps |
| T1240 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3478621807 |
|
|
Apr 21 12:40:16 PM PDT 24 |
Apr 21 12:40:31 PM PDT 24 |
28802500 ps |
| T1241 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.488323403 |
|
|
Apr 21 12:40:09 PM PDT 24 |
Apr 21 12:40:23 PM PDT 24 |
17479700 ps |
| T1242 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.2407307311 |
|
|
Apr 21 12:40:30 PM PDT 24 |
Apr 21 12:40:44 PM PDT 24 |
157909100 ps |
| T1243 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.2952007565 |
|
|
Apr 21 12:40:21 PM PDT 24 |
Apr 21 12:40:35 PM PDT 24 |
15953600 ps |
| T1244 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.151848376 |
|
|
Apr 21 12:40:19 PM PDT 24 |
Apr 21 12:40:36 PM PDT 24 |
21328100 ps |
| T1245 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.915162324 |
|
|
Apr 21 12:39:59 PM PDT 24 |
Apr 21 12:40:13 PM PDT 24 |
89682000 ps |
| T1246 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.842473079 |
|
|
Apr 21 12:40:10 PM PDT 24 |
Apr 21 12:40:27 PM PDT 24 |
126072300 ps |
| T1247 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2759376901 |
|
|
Apr 21 12:40:05 PM PDT 24 |
Apr 21 12:40:19 PM PDT 24 |
26036200 ps |
| T1248 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.3068820227 |
|
|
Apr 21 12:40:15 PM PDT 24 |
Apr 21 12:40:30 PM PDT 24 |
11573100 ps |
| T1249 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.1159591472 |
|
|
Apr 21 12:40:02 PM PDT 24 |
Apr 21 12:40:48 PM PDT 24 |
93341400 ps |
| T1250 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.619582018 |
|
|
Apr 21 12:40:02 PM PDT 24 |
Apr 21 12:40:20 PM PDT 24 |
29639600 ps |
| T1251 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.310520777 |
|
|
Apr 21 12:39:51 PM PDT 24 |
Apr 21 12:40:05 PM PDT 24 |
41845000 ps |
| T1252 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1189932921 |
|
|
Apr 21 12:40:15 PM PDT 24 |
Apr 21 12:40:31 PM PDT 24 |
55504000 ps |