Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	326868	1		T1	1		T2	2		T3	1335
all_values[1]	326868	1		T1	1		T2	2		T3	1335
all_values[2]	326868	1		T1	1		T2	2		T3	1335
all_values[3]	326868	1		T1	1		T2	2		T3	1335
all_values[4]	326868	1		T1	1		T2	2		T3	1335
all_values[5]	326868	1		T1	1		T2	2		T3	1335

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	660084	1		T1	6		T2	12		T3	2674
auto[1]	1301124	1		T3	5336		T14	6528		T20	4324

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	955362	1		T1	4		T2	6		T3	4006
auto[1]	1005846	1		T1	2		T2	6		T3	4004

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	326680	1		T1	1		T2	2		T3	1335
all_values[0]	auto[1]	auto[1]	188	1		T252	4		T253	1		T254	5
all_values[1]	auto[0]	auto[1]	326707	1		T1	1		T2	2		T3	1335
all_values[1]	auto[1]	auto[1]	161	1		T252	5		T253	2		T254	6
all_values[2]	auto[0]	auto[0]	1621	1		T1	1		T2	2		T3	1
all_values[2]	auto[0]	auto[1]	63	1		T252	1		T253	1		T254	1
all_values[2]	auto[1]	auto[0]	325121	1		T3	1334		T14	1632		T20	1081
all_values[2]	auto[1]	auto[1]	63	1		T252	1		T253	1		T254	2
all_values[3]	auto[0]	auto[0]	1616	1		T1	1		T2	2		T3	1
all_values[3]	auto[0]	auto[1]	59	1		T253	1		T254	3		T322	1
all_values[3]	auto[1]	auto[0]	72988	1		T3	667		T14	816		T20	1081
all_values[3]	auto[1]	auto[1]	252205	1		T3	667		T14	816		T28	1185
all_values[4]	auto[0]	auto[0]	1137	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	522	1		T2	1		T4	1		T5	1
all_values[4]	auto[1]	auto[0]	226220	1		T3	667		T14	816		T20	1
all_values[4]	auto[1]	auto[1]	98989	1		T3	667		T14	816		T20	1080
all_values[5]	auto[0]	auto[0]	1534	1		T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	145	1		T2	1		T31	1		T32	1
all_values[5]	auto[1]	auto[0]	325125	1		T3	1334		T14	1632		T20	1081
all_values[5]	auto[1]	auto[1]	64	1		T322	1		T323	3		T325	3