Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
201 |
1 |
|
T177 |
1 |
|
T386 |
1 |
|
T58 |
1 |
| others[1] |
202 |
1 |
|
T38 |
1 |
|
T67 |
5 |
|
T99 |
11 |
| others[2] |
237 |
1 |
|
T58 |
2 |
|
T97 |
1 |
|
T67 |
15 |
| others[3] |
353 |
1 |
|
T67 |
18 |
|
T89 |
1 |
|
T68 |
1 |
| false |
120 |
1 |
|
T67 |
5 |
|
T225 |
1 |
|
T99 |
2 |
| true |
13560 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9022 |
1 |
|
T3 |
1 |
|
T40 |
149 |
|
T56 |
2 |
| others[1] |
1268 |
1 |
|
T20 |
1 |
|
T34 |
1 |
|
T35 |
1 |
| others[2] |
1250 |
1 |
|
T62 |
1 |
|
T30 |
1 |
|
T34 |
7 |
| others[3] |
2051 |
1 |
|
T4 |
1 |
|
T14 |
1 |
|
T53 |
1 |
| false |
649 |
1 |
|
T16 |
1 |
|
T37 |
1 |
|
T32 |
1 |
| true |
433 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8990 |
1 |
|
T3 |
1 |
|
T40 |
149 |
|
T56 |
2 |
| others[1] |
1290 |
1 |
|
T16 |
1 |
|
T20 |
1 |
|
T34 |
3 |
| others[2] |
1255 |
1 |
|
T34 |
4 |
|
T102 |
1 |
|
T106 |
1 |
| others[3] |
2086 |
1 |
|
T4 |
1 |
|
T53 |
1 |
|
T37 |
1 |
| false |
628 |
1 |
|
T14 |
1 |
|
T62 |
1 |
|
T30 |
1 |
| true |
424 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
110 |
1 |
|
T62 |
1 |
|
T67 |
6 |
|
T89 |
1 |
| others[1] |
101 |
1 |
|
T177 |
1 |
|
T134 |
1 |
|
T67 |
3 |
| others[2] |
108 |
1 |
|
T62 |
1 |
|
T58 |
1 |
|
T67 |
3 |
| others[3] |
187 |
1 |
|
T386 |
2 |
|
T58 |
1 |
|
T67 |
6 |
| false |
55 |
1 |
|
T58 |
2 |
|
T99 |
3 |
|
T69 |
1 |
| true |
14112 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
251 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T67 |
8 |
| others[1] |
235 |
1 |
|
T31 |
1 |
|
T57 |
1 |
|
T67 |
8 |
| others[2] |
256 |
1 |
|
T15 |
1 |
|
T62 |
1 |
|
T28 |
1 |
| others[3] |
374 |
1 |
|
T38 |
1 |
|
T62 |
1 |
|
T30 |
1 |
| false |
119 |
1 |
|
T386 |
1 |
|
T67 |
6 |
|
T91 |
1 |
| true |
13438 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8882 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T15 |
1 |
| others[1] |
1048 |
1 |
|
T16 |
1 |
|
T10 |
1 |
|
T31 |
1 |
| others[2] |
1046 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T37 |
1 |
| others[3] |
1807 |
1 |
|
T38 |
1 |
|
T62 |
1 |
|
T34 |
5 |
| false |
538 |
1 |
|
T14 |
1 |
|
T34 |
4 |
|
T96 |
1 |
| true |
1352 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T28 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T31 |
1 |
|
T386 |
1 |
|
T58 |
1 |
| others[1] |
226 |
1 |
|
T62 |
1 |
|
T30 |
1 |
|
T386 |
1 |
| others[2] |
247 |
1 |
|
T58 |
1 |
|
T134 |
1 |
|
T67 |
15 |
| others[3] |
376 |
1 |
|
T38 |
1 |
|
T28 |
1 |
|
T177 |
1 |
| false |
130 |
1 |
|
T21 |
1 |
|
T67 |
5 |
|
T89 |
1 |
| true |
13473 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
219 |
1 |
|
T62 |
1 |
|
T30 |
1 |
|
T386 |
1 |
| others[1] |
241 |
1 |
|
T2 |
1 |
|
T320 |
1 |
|
T67 |
14 |
| others[2] |
234 |
1 |
|
T62 |
1 |
|
T67 |
9 |
|
T99 |
12 |
| others[3] |
365 |
1 |
|
T17 |
1 |
|
T177 |
1 |
|
T57 |
1 |
| false |
122 |
1 |
|
T67 |
6 |
|
T68 |
1 |
|
T99 |
11 |
| true |
13492 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9030 |
1 |
|
T2 |
1 |
|
T40 |
149 |
|
T56 |
2 |
| others[1] |
1225 |
1 |
|
T37 |
1 |
|
T20 |
1 |
|
T62 |
1 |
| others[2] |
1249 |
1 |
|
T14 |
1 |
|
T38 |
1 |
|
T28 |
1 |
| others[3] |
2087 |
1 |
|
T3 |
1 |
|
T32 |
1 |
|
T30 |
1 |
| false |
652 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T53 |
1 |
| true |
430 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1237 |
1 |
|
T3 |
1 |
|
T14 |
1 |
|
T16 |
1 |
| others[1] |
1264 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T62 |
1 |
| others[2] |
1271 |
1 |
|
T37 |
1 |
|
T30 |
1 |
|
T34 |
2 |
| others[3] |
2095 |
1 |
|
T53 |
1 |
|
T10 |
1 |
|
T62 |
1 |
| false |
655 |
1 |
|
T34 |
4 |
|
T103 |
1 |
|
T106 |
1 |
| true |
413 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
114 |
1 |
|
T2 |
1 |
|
T58 |
2 |
|
T67 |
5 |
| others[1] |
113 |
1 |
|
T386 |
1 |
|
T67 |
2 |
|
T91 |
1 |
| others[2] |
105 |
1 |
|
T62 |
1 |
|
T58 |
2 |
|
T67 |
4 |
| others[3] |
152 |
1 |
|
T386 |
1 |
|
T67 |
3 |
|
T387 |
1 |
| false |
48 |
1 |
|
T62 |
1 |
|
T67 |
2 |
|
T99 |
2 |
| true |
6403 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
214 |
1 |
|
T2 |
1 |
|
T33 |
1 |
|
T58 |
1 |
| others[1] |
241 |
1 |
|
T17 |
1 |
|
T386 |
1 |
|
T67 |
8 |
| others[2] |
231 |
1 |
|
T177 |
1 |
|
T67 |
13 |
|
T91 |
1 |
| others[3] |
440 |
1 |
|
T28 |
1 |
|
T57 |
1 |
|
T320 |
1 |
| false |
120 |
1 |
|
T386 |
1 |
|
T67 |
10 |
|
T99 |
6 |
| true |
5689 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1047 |
1 |
|
T4 |
1 |
|
T34 |
3 |
|
T96 |
1 |
| others[1] |
1090 |
1 |
|
T16 |
1 |
|
T37 |
1 |
|
T34 |
3 |
| others[2] |
1092 |
1 |
|
T17 |
1 |
|
T10 |
1 |
|
T30 |
1 |
| others[3] |
1740 |
1 |
|
T3 |
1 |
|
T15 |
1 |
|
T53 |
1 |
| false |
566 |
1 |
|
T14 |
1 |
|
T32 |
1 |
|
T34 |
4 |
| true |
1400 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
247 |
1 |
|
T67 |
15 |
|
T99 |
9 |
|
T208 |
1 |
| others[1] |
209 |
1 |
|
T67 |
7 |
|
T99 |
7 |
|
T49 |
1 |
| others[2] |
230 |
1 |
|
T62 |
1 |
|
T320 |
1 |
|
T58 |
1 |
| others[3] |
377 |
1 |
|
T21 |
1 |
|
T386 |
1 |
|
T97 |
1 |
| false |
112 |
1 |
|
T31 |
1 |
|
T67 |
7 |
|
T99 |
9 |
| true |
5760 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
202 |
1 |
|
T38 |
1 |
|
T31 |
1 |
|
T30 |
1 |
| others[1] |
245 |
1 |
|
T177 |
1 |
|
T320 |
1 |
|
T67 |
14 |
| others[2] |
229 |
1 |
|
T67 |
9 |
|
T387 |
1 |
|
T99 |
7 |
| others[3] |
380 |
1 |
|
T97 |
1 |
|
T134 |
1 |
|
T67 |
24 |
| false |
105 |
1 |
|
T2 |
1 |
|
T67 |
6 |
|
T387 |
1 |
| true |
5774 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1272 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T53 |
1 |
| others[1] |
1253 |
1 |
|
T37 |
1 |
|
T32 |
1 |
|
T34 |
5 |
| others[2] |
1248 |
1 |
|
T62 |
1 |
|
T30 |
1 |
|
T34 |
2 |
| others[3] |
2089 |
1 |
|
T3 |
1 |
|
T14 |
1 |
|
T34 |
10 |
| false |
630 |
1 |
|
T185 |
1 |
|
T66 |
1 |
|
T58 |
1 |
| true |
443 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1290 |
1 |
|
T14 |
1 |
|
T53 |
1 |
|
T20 |
1 |
| others[1] |
1218 |
1 |
|
T62 |
1 |
|
T34 |
4 |
|
T102 |
1 |
| others[2] |
1261 |
1 |
|
T30 |
1 |
|
T177 |
1 |
|
T34 |
6 |
| others[3] |
2096 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T37 |
1 |
| false |
644 |
1 |
|
T16 |
1 |
|
T34 |
3 |
|
T95 |
1 |
| true |
426 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
99 |
1 |
|
T30 |
1 |
|
T67 |
3 |
|
T387 |
1 |
| others[1] |
95 |
1 |
|
T58 |
1 |
|
T67 |
3 |
|
T89 |
1 |
| others[2] |
102 |
1 |
|
T62 |
2 |
|
T58 |
1 |
|
T67 |
6 |
| others[3] |
187 |
1 |
|
T386 |
2 |
|
T58 |
1 |
|
T67 |
9 |
| false |
58 |
1 |
|
T58 |
1 |
|
T67 |
3 |
|
T388 |
1 |
| true |
6394 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T58 |
1 |
|
T204 |
1 |
|
T67 |
12 |
| others[1] |
232 |
1 |
|
T62 |
1 |
|
T67 |
11 |
|
T390 |
1 |
| others[2] |
222 |
1 |
|
T2 |
1 |
|
T62 |
1 |
|
T67 |
12 |
| others[3] |
409 |
1 |
|
T15 |
1 |
|
T17 |
1 |
|
T38 |
1 |
| false |
114 |
1 |
|
T67 |
2 |
|
T99 |
2 |
|
T391 |
1 |
| true |
5727 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1056 |
1 |
|
T17 |
1 |
|
T10 |
1 |
|
T38 |
1 |
| others[1] |
1064 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T177 |
1 |
| others[2] |
1119 |
1 |
|
T14 |
1 |
|
T5 |
1 |
|
T30 |
1 |
| others[3] |
1743 |
1 |
|
T3 |
1 |
|
T37 |
1 |
|
T31 |
1 |
| false |
539 |
1 |
|
T53 |
1 |
|
T62 |
1 |
|
T34 |
1 |
| true |
1414 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T67 |
7 |
|
T99 |
12 |
|
T389 |
1 |
| others[1] |
226 |
1 |
|
T62 |
1 |
|
T30 |
1 |
|
T67 |
10 |
| others[2] |
231 |
1 |
|
T177 |
1 |
|
T58 |
1 |
|
T67 |
11 |
| others[3] |
371 |
1 |
|
T15 |
1 |
|
T31 |
1 |
|
T320 |
1 |
| false |
120 |
1 |
|
T58 |
1 |
|
T97 |
1 |
|
T67 |
5 |
| true |
5763 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
205 |
1 |
|
T58 |
1 |
|
T67 |
10 |
|
T387 |
1 |
| others[1] |
210 |
1 |
|
T386 |
1 |
|
T97 |
1 |
|
T67 |
7 |
| others[2] |
246 |
1 |
|
T62 |
1 |
|
T134 |
1 |
|
T67 |
10 |
| others[3] |
388 |
1 |
|
T2 |
1 |
|
T177 |
1 |
|
T67 |
18 |
| false |
122 |
1 |
|
T57 |
1 |
|
T67 |
5 |
|
T99 |
7 |
| true |
5764 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1234 |
1 |
|
T4 |
1 |
|
T14 |
1 |
|
T37 |
1 |
| others[1] |
1238 |
1 |
|
T34 |
4 |
|
T106 |
1 |
|
T35 |
1 |
| others[2] |
1232 |
1 |
|
T3 |
1 |
|
T53 |
1 |
|
T62 |
1 |
| others[3] |
2078 |
1 |
|
T20 |
1 |
|
T30 |
1 |
|
T177 |
1 |
| false |
714 |
1 |
|
T16 |
1 |
|
T34 |
4 |
|
T66 |
3 |
| true |
439 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1236 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T53 |
1 |
| others[1] |
1267 |
1 |
|
T16 |
1 |
|
T20 |
1 |
|
T30 |
1 |
| others[2] |
1278 |
1 |
|
T14 |
1 |
|
T62 |
1 |
|
T177 |
1 |
| others[3] |
2119 |
1 |
|
T62 |
1 |
|
T32 |
1 |
|
T34 |
5 |
| false |
617 |
1 |
|
T34 |
3 |
|
T103 |
1 |
|
T202 |
3 |
| true |
418 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
112 |
1 |
|
T62 |
1 |
|
T58 |
1 |
|
T67 |
3 |
| others[1] |
93 |
1 |
|
T58 |
1 |
|
T67 |
4 |
|
T388 |
1 |
| others[2] |
100 |
1 |
|
T386 |
1 |
|
T58 |
1 |
|
T67 |
3 |
| others[3] |
192 |
1 |
|
T62 |
1 |
|
T30 |
1 |
|
T58 |
1 |
| false |
58 |
1 |
|
T386 |
1 |
|
T67 |
3 |
|
T225 |
1 |
| true |
6380 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
255 |
1 |
|
T2 |
1 |
|
T57 |
1 |
|
T22 |
1 |
| others[1] |
237 |
1 |
|
T28 |
1 |
|
T386 |
1 |
|
T58 |
1 |
| others[2] |
237 |
1 |
|
T58 |
1 |
|
T97 |
1 |
|
T67 |
10 |
| others[3] |
429 |
1 |
|
T15 |
1 |
|
T19 |
1 |
|
T38 |
1 |
| false |
109 |
1 |
|
T58 |
1 |
|
T67 |
5 |
|
T48 |
1 |
| true |
5668 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1063 |
1 |
|
T20 |
1 |
|
T62 |
1 |
|
T30 |
1 |
| others[1] |
1100 |
1 |
|
T15 |
1 |
|
T37 |
1 |
|
T34 |
1 |
| others[2] |
1051 |
1 |
|
T2 |
1 |
|
T14 |
1 |
|
T53 |
1 |
| others[3] |
1770 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T19 |
1 |
| false |
554 |
1 |
|
T1 |
1 |
|
T16 |
1 |
|
T34 |
1 |
| true |
1397 |
1 |
|
T5 |
1 |
|
T17 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T17 |
1 |
|
T177 |
1 |
|
T67 |
7 |
| others[1] |
229 |
1 |
|
T57 |
1 |
|
T67 |
12 |
|
T29 |
1 |
| others[2] |
237 |
1 |
|
T2 |
1 |
|
T320 |
1 |
|
T58 |
1 |
| others[3] |
389 |
1 |
|
T62 |
1 |
|
T30 |
1 |
|
T67 |
18 |
| false |
132 |
1 |
|
T31 |
1 |
|
T67 |
5 |
|
T388 |
1 |
| true |
5727 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
215 |
1 |
|
T17 |
1 |
|
T57 |
1 |
|
T386 |
1 |
| others[1] |
231 |
1 |
|
T2 |
1 |
|
T62 |
1 |
|
T67 |
11 |
| others[2] |
204 |
1 |
|
T58 |
1 |
|
T67 |
10 |
|
T388 |
1 |
| others[3] |
399 |
1 |
|
T38 |
1 |
|
T320 |
1 |
|
T58 |
2 |
| false |
120 |
1 |
|
T30 |
1 |
|
T67 |
5 |
|
T99 |
8 |
| true |
5766 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1334 |
1 |
|
T3 |
1 |
|
T37 |
1 |
|
T62 |
1 |
| others[1] |
1227 |
1 |
|
T4 |
1 |
|
T62 |
1 |
|
T34 |
5 |
| others[2] |
1263 |
1 |
|
T14 |
1 |
|
T15 |
1 |
|
T17 |
1 |
| others[3] |
2033 |
1 |
|
T16 |
1 |
|
T53 |
1 |
|
T20 |
1 |
| false |
654 |
1 |
|
T32 |
1 |
|
T34 |
2 |
|
T95 |
1 |
| true |
424 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1278 |
1 |
|
T53 |
1 |
|
T20 |
1 |
|
T30 |
1 |
| others[1] |
1263 |
1 |
|
T37 |
1 |
|
T62 |
1 |
|
T34 |
5 |
| others[2] |
1250 |
1 |
|
T14 |
1 |
|
T19 |
1 |
|
T32 |
1 |
| others[3] |
2092 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T62 |
1 |
| false |
640 |
1 |
|
T4 |
1 |
|
T34 |
3 |
|
T66 |
1 |
| true |
412 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |