Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
122 |
1 |
|
T62 |
1 |
|
T58 |
1 |
|
T67 |
9 |
| others[1] |
102 |
1 |
|
T62 |
1 |
|
T67 |
3 |
|
T89 |
1 |
| others[2] |
100 |
1 |
|
T67 |
2 |
|
T387 |
1 |
|
T99 |
4 |
| others[3] |
170 |
1 |
|
T386 |
2 |
|
T58 |
2 |
|
T67 |
6 |
| false |
50 |
1 |
|
T58 |
1 |
|
T67 |
3 |
|
T69 |
1 |
| true |
6391 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
255 |
1 |
|
T177 |
1 |
|
T67 |
12 |
|
T29 |
1 |
| others[1] |
237 |
1 |
|
T17 |
1 |
|
T31 |
1 |
|
T62 |
1 |
| others[2] |
232 |
1 |
|
T19 |
1 |
|
T30 |
1 |
|
T320 |
1 |
| others[3] |
391 |
1 |
|
T38 |
1 |
|
T21 |
1 |
|
T33 |
1 |
| false |
121 |
1 |
|
T204 |
1 |
|
T67 |
3 |
|
T99 |
6 |
| true |
5699 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1049 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T53 |
1 |
| others[1] |
1057 |
1 |
|
T3 |
1 |
|
T62 |
1 |
|
T177 |
1 |
| others[2] |
1104 |
1 |
|
T31 |
1 |
|
T20 |
1 |
|
T62 |
1 |
| others[3] |
1777 |
1 |
|
T4 |
1 |
|
T14 |
1 |
|
T15 |
1 |
| false |
541 |
1 |
|
T16 |
1 |
|
T30 |
1 |
|
T34 |
2 |
| true |
1407 |
1 |
|
T1 |
1 |
|
T17 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T15 |
1 |
|
T62 |
1 |
|
T320 |
1 |
| others[1] |
225 |
1 |
|
T58 |
1 |
|
T67 |
9 |
|
T388 |
1 |
| others[2] |
239 |
1 |
|
T58 |
1 |
|
T67 |
9 |
|
T99 |
10 |
| others[3] |
389 |
1 |
|
T30 |
1 |
|
T386 |
1 |
|
T58 |
1 |
| false |
138 |
1 |
|
T67 |
6 |
|
T99 |
7 |
|
T69 |
7 |
| true |
5716 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
223 |
1 |
|
T62 |
1 |
|
T30 |
1 |
|
T320 |
1 |
| others[1] |
235 |
1 |
|
T67 |
5 |
|
T99 |
12 |
|
T392 |
1 |
| others[2] |
235 |
1 |
|
T31 |
1 |
|
T177 |
1 |
|
T58 |
1 |
| others[3] |
396 |
1 |
|
T67 |
21 |
|
T91 |
1 |
|
T388 |
2 |
| false |
108 |
1 |
|
T38 |
1 |
|
T58 |
1 |
|
T134 |
1 |
| true |
5738 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1259 |
1 |
|
T15 |
1 |
|
T19 |
1 |
|
T62 |
1 |
| others[1] |
1233 |
1 |
|
T20 |
1 |
|
T32 |
1 |
|
T30 |
1 |
| others[2] |
1284 |
1 |
|
T3 |
1 |
|
T14 |
1 |
|
T53 |
1 |
| others[3] |
2084 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T37 |
1 |
| false |
633 |
1 |
|
T34 |
2 |
|
T386 |
1 |
|
T58 |
1 |
| true |
442 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1261 |
1 |
|
T53 |
1 |
|
T62 |
1 |
|
T34 |
4 |
| others[1] |
1209 |
1 |
|
T3 |
1 |
|
T14 |
1 |
|
T20 |
1 |
| others[2] |
1270 |
1 |
|
T62 |
1 |
|
T30 |
1 |
|
T34 |
4 |
| others[3] |
2139 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T37 |
1 |
| false |
635 |
1 |
|
T34 |
1 |
|
T126 |
1 |
|
T66 |
2 |
| true |
421 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
88 |
1 |
|
T62 |
1 |
|
T386 |
1 |
|
T67 |
3 |
| others[1] |
105 |
1 |
|
T58 |
1 |
|
T67 |
6 |
|
T89 |
1 |
| others[2] |
101 |
1 |
|
T62 |
1 |
|
T386 |
1 |
|
T58 |
2 |
| others[3] |
174 |
1 |
|
T67 |
8 |
|
T89 |
1 |
|
T91 |
1 |
| false |
54 |
1 |
|
T58 |
1 |
|
T67 |
1 |
|
T99 |
1 |
| true |
6413 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T97 |
1 |
|
T67 |
12 |
|
T89 |
1 |
| others[1] |
254 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T17 |
1 |
| others[2] |
260 |
1 |
|
T31 |
1 |
|
T58 |
2 |
|
T67 |
10 |
| others[3] |
395 |
1 |
|
T62 |
1 |
|
T30 |
1 |
|
T67 |
16 |
| false |
110 |
1 |
|
T177 |
1 |
|
T67 |
5 |
|
T99 |
2 |
| true |
5689 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1065 |
1 |
|
T14 |
1 |
|
T34 |
4 |
|
T106 |
1 |
| others[1] |
1066 |
1 |
|
T1 |
1 |
|
T53 |
1 |
|
T62 |
1 |
| others[2] |
1040 |
1 |
|
T16 |
1 |
|
T34 |
6 |
|
T21 |
1 |
| others[3] |
1819 |
1 |
|
T4 |
1 |
|
T15 |
1 |
|
T37 |
1 |
| false |
523 |
1 |
|
T3 |
1 |
|
T34 |
4 |
|
T103 |
1 |
| true |
1422 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
234 |
1 |
|
T57 |
1 |
|
T67 |
14 |
|
T99 |
11 |
| others[1] |
232 |
1 |
|
T15 |
1 |
|
T58 |
1 |
|
T67 |
10 |
| others[2] |
214 |
1 |
|
T31 |
1 |
|
T320 |
1 |
|
T386 |
1 |
| others[3] |
397 |
1 |
|
T62 |
1 |
|
T177 |
1 |
|
T67 |
10 |
| false |
137 |
1 |
|
T67 |
5 |
|
T99 |
8 |
|
T69 |
4 |
| true |
5721 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
201 |
1 |
|
T67 |
4 |
|
T99 |
9 |
|
T392 |
1 |
| others[1] |
204 |
1 |
|
T17 |
1 |
|
T38 |
1 |
|
T67 |
8 |
| others[2] |
211 |
1 |
|
T177 |
1 |
|
T67 |
9 |
|
T388 |
1 |
| others[3] |
374 |
1 |
|
T62 |
1 |
|
T386 |
1 |
|
T67 |
22 |
| false |
102 |
1 |
|
T67 |
5 |
|
T89 |
1 |
|
T99 |
2 |
| true |
5843 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1255 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T34 |
4 |
| others[1] |
1265 |
1 |
|
T32 |
2 |
|
T34 |
4 |
|
T103 |
1 |
| others[2] |
1218 |
1 |
|
T4 |
1 |
|
T15 |
1 |
|
T53 |
1 |
| others[3] |
2101 |
1 |
|
T3 |
1 |
|
T37 |
1 |
|
T20 |
1 |
| false |
662 |
1 |
|
T17 |
1 |
|
T34 |
4 |
|
T35 |
1 |
| true |
434 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1230 |
1 |
|
T53 |
1 |
|
T32 |
1 |
|
T30 |
1 |
| others[1] |
1235 |
1 |
|
T4 |
1 |
|
T34 |
8 |
|
T95 |
1 |
| others[2] |
1254 |
1 |
|
T62 |
1 |
|
T34 |
3 |
|
T35 |
2 |
| others[3] |
2086 |
1 |
|
T16 |
1 |
|
T37 |
1 |
|
T20 |
1 |
| false |
703 |
1 |
|
T3 |
1 |
|
T14 |
1 |
|
T62 |
1 |
| true |
427 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
105 |
1 |
|
T62 |
1 |
|
T386 |
1 |
|
T67 |
6 |
| others[1] |
95 |
1 |
|
T58 |
2 |
|
T67 |
5 |
|
T388 |
1 |
| others[2] |
111 |
1 |
|
T62 |
1 |
|
T58 |
1 |
|
T67 |
6 |
| others[3] |
179 |
1 |
|
T2 |
1 |
|
T386 |
1 |
|
T58 |
1 |
| false |
57 |
1 |
|
T67 |
3 |
|
T99 |
2 |
|
T69 |
1 |
| true |
6388 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
245 |
1 |
|
T15 |
1 |
|
T17 |
1 |
|
T19 |
1 |
| others[1] |
240 |
1 |
|
T2 |
1 |
|
T30 |
1 |
|
T67 |
7 |
| others[2] |
247 |
1 |
|
T38 |
1 |
|
T67 |
7 |
|
T99 |
10 |
| others[3] |
395 |
1 |
|
T386 |
1 |
|
T67 |
18 |
|
T91 |
1 |
| false |
136 |
1 |
|
T67 |
6 |
|
T99 |
5 |
|
T69 |
4 |
| true |
5672 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1043 |
1 |
|
T4 |
1 |
|
T34 |
5 |
|
T96 |
1 |
| others[1] |
1079 |
1 |
|
T5 |
1 |
|
T16 |
1 |
|
T53 |
1 |
| others[2] |
1067 |
1 |
|
T14 |
1 |
|
T17 |
1 |
|
T62 |
2 |
| others[3] |
1796 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T15 |
1 |
| false |
556 |
1 |
|
T34 |
2 |
|
T66 |
1 |
|
T202 |
1 |
| true |
1394 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T2 |
1 |
|
T62 |
1 |
|
T320 |
1 |
| others[1] |
235 |
1 |
|
T67 |
9 |
|
T91 |
1 |
|
T48 |
1 |
| others[2] |
244 |
1 |
|
T38 |
1 |
|
T30 |
1 |
|
T177 |
1 |
| others[3] |
381 |
1 |
|
T31 |
1 |
|
T57 |
1 |
|
T67 |
16 |
| false |
115 |
1 |
|
T62 |
1 |
|
T67 |
2 |
|
T387 |
1 |
| true |
5719 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T177 |
1 |
|
T320 |
1 |
|
T386 |
1 |
| others[1] |
214 |
1 |
|
T58 |
1 |
|
T67 |
6 |
|
T225 |
1 |
| others[2] |
202 |
1 |
|
T58 |
1 |
|
T67 |
9 |
|
T99 |
13 |
| others[3] |
314 |
1 |
|
T31 |
1 |
|
T57 |
1 |
|
T386 |
1 |
| false |
137 |
1 |
|
T2 |
1 |
|
T38 |
1 |
|
T67 |
6 |
| true |
5829 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1241 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T16 |
1 |
| others[1] |
1306 |
1 |
|
T4 |
1 |
|
T37 |
1 |
|
T20 |
1 |
| others[2] |
1222 |
1 |
|
T53 |
1 |
|
T62 |
1 |
|
T57 |
1 |
| others[3] |
2045 |
1 |
|
T14 |
1 |
|
T17 |
1 |
|
T28 |
1 |
| false |
673 |
1 |
|
T96 |
1 |
|
T35 |
1 |
|
T66 |
3 |
| true |
448 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1295 |
1 |
|
T4 |
1 |
|
T37 |
1 |
|
T34 |
5 |
| others[1] |
1270 |
1 |
|
T34 |
3 |
|
T66 |
4 |
|
T386 |
1 |
| others[2] |
1260 |
1 |
|
T16 |
1 |
|
T62 |
2 |
|
T34 |
2 |
| others[3] |
2040 |
1 |
|
T3 |
1 |
|
T14 |
1 |
|
T20 |
1 |
| false |
640 |
1 |
|
T53 |
1 |
|
T19 |
1 |
|
T30 |
1 |
| true |
430 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
99 |
1 |
|
T62 |
1 |
|
T58 |
3 |
|
T67 |
3 |
| others[1] |
109 |
1 |
|
T67 |
4 |
|
T89 |
1 |
|
T388 |
1 |
| others[2] |
107 |
1 |
|
T62 |
1 |
|
T58 |
1 |
|
T67 |
5 |
| others[3] |
162 |
1 |
|
T30 |
1 |
|
T386 |
1 |
|
T67 |
5 |
| false |
43 |
1 |
|
T386 |
1 |
|
T99 |
2 |
|
T69 |
3 |
| true |
6415 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T2 |
1 |
|
T28 |
1 |
|
T67 |
10 |
| others[1] |
239 |
1 |
|
T62 |
1 |
|
T204 |
1 |
|
T67 |
9 |
| others[2] |
233 |
1 |
|
T58 |
1 |
|
T67 |
12 |
|
T99 |
6 |
| others[3] |
405 |
1 |
|
T22 |
1 |
|
T386 |
1 |
|
T67 |
21 |
| false |
144 |
1 |
|
T38 |
1 |
|
T67 |
6 |
|
T387 |
1 |
| true |
5682 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1073 |
1 |
|
T28 |
1 |
|
T30 |
1 |
|
T177 |
1 |
| others[1] |
1066 |
1 |
|
T62 |
1 |
|
T34 |
5 |
|
T21 |
1 |
| others[2] |
1082 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
| others[3] |
1818 |
1 |
|
T14 |
1 |
|
T15 |
1 |
|
T16 |
1 |
| false |
536 |
1 |
|
T34 |
2 |
|
T35 |
1 |
|
T66 |
2 |
| true |
1360 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T2 |
1 |
|
T58 |
1 |
|
T97 |
1 |
| others[1] |
227 |
1 |
|
T15 |
1 |
|
T62 |
1 |
|
T28 |
1 |
| others[2] |
235 |
1 |
|
T62 |
1 |
|
T67 |
8 |
|
T99 |
8 |
| others[3] |
396 |
1 |
|
T57 |
1 |
|
T134 |
1 |
|
T67 |
13 |
| false |
121 |
1 |
|
T67 |
2 |
|
T277 |
1 |
|
T99 |
4 |
| true |
5728 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
210 |
1 |
|
T177 |
1 |
|
T57 |
1 |
|
T67 |
12 |
| others[1] |
206 |
1 |
|
T67 |
7 |
|
T99 |
9 |
|
T137 |
1 |
| others[2] |
251 |
1 |
|
T58 |
1 |
|
T67 |
10 |
|
T89 |
1 |
| others[3] |
362 |
1 |
|
T17 |
1 |
|
T30 |
1 |
|
T386 |
1 |
| false |
92 |
1 |
|
T67 |
4 |
|
T99 |
5 |
|
T69 |
4 |
| true |
5814 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1222 |
1 |
|
T4 |
1 |
|
T14 |
1 |
|
T53 |
1 |
| others[1] |
1254 |
1 |
|
T17 |
1 |
|
T30 |
1 |
|
T34 |
5 |
| others[2] |
1193 |
1 |
|
T62 |
1 |
|
T34 |
3 |
|
T96 |
1 |
| others[3] |
2140 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T37 |
1 |
| false |
686 |
1 |
|
T15 |
1 |
|
T32 |
1 |
|
T34 |
3 |
| true |
440 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1213 |
1 |
|
T16 |
1 |
|
T20 |
1 |
|
T62 |
1 |
| others[1] |
1215 |
1 |
|
T14 |
1 |
|
T34 |
3 |
|
T185 |
1 |
| others[2] |
1316 |
1 |
|
T62 |
1 |
|
T30 |
1 |
|
T34 |
3 |
| others[3] |
2086 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T53 |
1 |
| false |
677 |
1 |
|
T37 |
1 |
|
T34 |
2 |
|
T106 |
1 |
| true |
428 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
117 |
1 |
|
T62 |
1 |
|
T58 |
1 |
|
T134 |
1 |
| others[1] |
110 |
1 |
|
T386 |
1 |
|
T58 |
2 |
|
T67 |
8 |
| others[2] |
101 |
1 |
|
T67 |
5 |
|
T91 |
1 |
|
T388 |
1 |
| others[3] |
156 |
1 |
|
T62 |
1 |
|
T30 |
1 |
|
T386 |
1 |
| false |
50 |
1 |
|
T58 |
1 |
|
T67 |
1 |
|
T225 |
1 |
| true |
6401 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T2 |
1 |
|
T31 |
1 |
|
T62 |
1 |
| others[1] |
248 |
1 |
|
T17 |
1 |
|
T62 |
1 |
|
T134 |
1 |
| others[2] |
237 |
1 |
|
T30 |
1 |
|
T386 |
1 |
|
T67 |
7 |
| others[3] |
399 |
1 |
|
T15 |
1 |
|
T28 |
1 |
|
T22 |
1 |
| false |
128 |
1 |
|
T58 |
1 |
|
T67 |
3 |
|
T99 |
4 |
| true |
5682 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1083 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T37 |
1 |
| others[1] |
1047 |
1 |
|
T15 |
1 |
|
T28 |
1 |
|
T34 |
3 |
| others[2] |
1052 |
1 |
|
T3 |
1 |
|
T14 |
1 |
|
T17 |
1 |
| others[3] |
1772 |
1 |
|
T5 |
1 |
|
T16 |
1 |
|
T62 |
2 |
| false |
594 |
1 |
|
T4 |
1 |
|
T32 |
2 |
|
T34 |
1 |
| true |
1387 |
1 |
|
T10 |
1 |
|
T19 |
1 |
|
T38 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |