Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T58 |
1 |
|
T67 |
6 |
|
T99 |
11 |
| others[1] |
218 |
1 |
|
T17 |
1 |
|
T58 |
1 |
|
T67 |
11 |
| others[2] |
239 |
1 |
|
T62 |
1 |
|
T320 |
1 |
|
T67 |
4 |
| others[3] |
389 |
1 |
|
T15 |
1 |
|
T31 |
1 |
|
T57 |
1 |
| false |
123 |
1 |
|
T67 |
2 |
|
T388 |
1 |
|
T387 |
1 |
| true |
5748 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
217 |
1 |
|
T38 |
1 |
|
T386 |
1 |
|
T58 |
1 |
| others[1] |
216 |
1 |
|
T67 |
13 |
|
T387 |
1 |
|
T205 |
1 |
| others[2] |
228 |
1 |
|
T67 |
9 |
|
T388 |
1 |
|
T387 |
1 |
| others[3] |
373 |
1 |
|
T30 |
1 |
|
T386 |
1 |
|
T58 |
2 |
| false |
112 |
1 |
|
T2 |
1 |
|
T67 |
3 |
|
T48 |
1 |
| true |
5789 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1189 |
1 |
|
T62 |
1 |
|
T32 |
1 |
|
T30 |
1 |
| others[1] |
1291 |
1 |
|
T3 |
1 |
|
T14 |
1 |
|
T34 |
4 |
| others[2] |
1300 |
1 |
|
T53 |
1 |
|
T37 |
1 |
|
T28 |
1 |
| others[3] |
2080 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T15 |
1 |
| false |
647 |
1 |
|
T16 |
1 |
|
T34 |
2 |
|
T66 |
3 |
| true |
428 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1259 |
1 |
|
T15 |
1 |
|
T34 |
3 |
|
T35 |
2 |
| others[1] |
1298 |
1 |
|
T16 |
1 |
|
T30 |
1 |
|
T34 |
3 |
| others[2] |
1210 |
1 |
|
T3 |
1 |
|
T53 |
1 |
|
T37 |
1 |
| others[3] |
2064 |
1 |
|
T20 |
1 |
|
T62 |
1 |
|
T34 |
7 |
| false |
676 |
1 |
|
T4 |
1 |
|
T14 |
1 |
|
T10 |
1 |
| true |
428 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
93 |
1 |
|
T58 |
2 |
|
T67 |
4 |
|
T388 |
1 |
| others[1] |
111 |
1 |
|
T386 |
1 |
|
T67 |
6 |
|
T89 |
1 |
| others[2] |
92 |
1 |
|
T386 |
1 |
|
T67 |
4 |
|
T387 |
1 |
| others[3] |
196 |
1 |
|
T62 |
2 |
|
T58 |
1 |
|
T67 |
10 |
| false |
58 |
1 |
|
T58 |
1 |
|
T387 |
1 |
|
T99 |
3 |
| true |
6385 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
219 |
1 |
|
T28 |
1 |
|
T177 |
1 |
|
T58 |
1 |
| others[1] |
219 |
1 |
|
T31 |
1 |
|
T320 |
1 |
|
T97 |
1 |
| others[2] |
233 |
1 |
|
T67 |
12 |
|
T205 |
1 |
|
T99 |
10 |
| others[3] |
388 |
1 |
|
T58 |
1 |
|
T67 |
15 |
|
T89 |
1 |
| false |
135 |
1 |
|
T67 |
6 |
|
T99 |
8 |
|
T69 |
6 |
| true |
5741 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1113 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
| others[1] |
999 |
1 |
|
T10 |
1 |
|
T34 |
2 |
|
T22 |
1 |
| others[2] |
1090 |
1 |
|
T15 |
1 |
|
T34 |
4 |
|
T95 |
1 |
| others[3] |
1771 |
1 |
|
T14 |
1 |
|
T5 |
1 |
|
T37 |
1 |
| false |
565 |
1 |
|
T16 |
1 |
|
T53 |
1 |
|
T34 |
4 |
| true |
1397 |
1 |
|
T1 |
1 |
|
T17 |
1 |
|
T38 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
230 |
1 |
|
T67 |
9 |
|
T99 |
10 |
|
T49 |
1 |
| others[1] |
226 |
1 |
|
T67 |
9 |
|
T99 |
9 |
|
T49 |
3 |
| others[2] |
243 |
1 |
|
T67 |
4 |
|
T390 |
1 |
|
T99 |
7 |
| others[3] |
392 |
1 |
|
T2 |
1 |
|
T31 |
1 |
|
T62 |
2 |
| false |
114 |
1 |
|
T57 |
1 |
|
T58 |
1 |
|
T67 |
9 |
| true |
5730 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T62 |
1 |
|
T30 |
1 |
|
T386 |
1 |
| others[1] |
222 |
1 |
|
T31 |
1 |
|
T58 |
1 |
|
T67 |
12 |
| others[2] |
210 |
1 |
|
T2 |
1 |
|
T58 |
1 |
|
T134 |
1 |
| others[3] |
362 |
1 |
|
T38 |
1 |
|
T67 |
13 |
|
T89 |
1 |
| false |
126 |
1 |
|
T67 |
4 |
|
T91 |
1 |
|
T99 |
8 |
| true |
5782 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1292 |
1 |
|
T53 |
1 |
|
T34 |
7 |
|
T66 |
2 |
| others[1] |
1245 |
1 |
|
T3 |
1 |
|
T38 |
1 |
|
T32 |
1 |
| others[2] |
1245 |
1 |
|
T16 |
1 |
|
T37 |
1 |
|
T34 |
2 |
| others[3] |
2078 |
1 |
|
T14 |
1 |
|
T19 |
1 |
|
T20 |
1 |
| false |
630 |
1 |
|
T4 |
1 |
|
T32 |
1 |
|
T34 |
1 |
| true |
445 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1217 |
1 |
|
T53 |
1 |
|
T10 |
1 |
|
T34 |
3 |
| others[1] |
1211 |
1 |
|
T20 |
1 |
|
T62 |
1 |
|
T34 |
6 |
| others[2] |
1299 |
1 |
|
T4 |
1 |
|
T28 |
1 |
|
T30 |
1 |
| others[3] |
2141 |
1 |
|
T14 |
1 |
|
T15 |
1 |
|
T16 |
1 |
| false |
646 |
1 |
|
T3 |
1 |
|
T34 |
2 |
|
T102 |
1 |
| true |
421 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
103 |
1 |
|
T30 |
1 |
|
T58 |
2 |
|
T67 |
6 |
| others[1] |
96 |
1 |
|
T386 |
2 |
|
T58 |
1 |
|
T67 |
4 |
| others[2] |
107 |
1 |
|
T62 |
1 |
|
T67 |
3 |
|
T89 |
1 |
| others[3] |
178 |
1 |
|
T31 |
1 |
|
T62 |
1 |
|
T58 |
1 |
| false |
60 |
1 |
|
T67 |
2 |
|
T99 |
5 |
|
T69 |
3 |
| true |
6391 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T19 |
1 |
|
T62 |
1 |
|
T33 |
1 |
| others[1] |
218 |
1 |
|
T2 |
1 |
|
T62 |
1 |
|
T67 |
6 |
| others[2] |
231 |
1 |
|
T67 |
16 |
|
T99 |
13 |
|
T391 |
1 |
| others[3] |
401 |
1 |
|
T17 |
1 |
|
T28 |
1 |
|
T386 |
1 |
| false |
135 |
1 |
|
T38 |
1 |
|
T67 |
9 |
|
T99 |
9 |
| true |
5721 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1034 |
1 |
|
T16 |
1 |
|
T53 |
1 |
|
T34 |
4 |
| others[1] |
1091 |
1 |
|
T3 |
1 |
|
T38 |
1 |
|
T177 |
1 |
| others[2] |
1028 |
1 |
|
T4 |
1 |
|
T34 |
4 |
|
T35 |
2 |
| others[3] |
1825 |
1 |
|
T14 |
1 |
|
T5 |
1 |
|
T37 |
1 |
| false |
539 |
1 |
|
T62 |
1 |
|
T34 |
2 |
|
T95 |
1 |
| true |
1418 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T57 |
1 |
|
T67 |
8 |
|
T205 |
1 |
| others[1] |
205 |
1 |
|
T67 |
6 |
|
T91 |
1 |
|
T68 |
1 |
| others[2] |
232 |
1 |
|
T58 |
1 |
|
T67 |
7 |
|
T388 |
1 |
| others[3] |
351 |
1 |
|
T17 |
1 |
|
T38 |
1 |
|
T177 |
1 |
| false |
124 |
1 |
|
T67 |
7 |
|
T277 |
1 |
|
T225 |
1 |
| true |
5796 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
207 |
1 |
|
T58 |
1 |
|
T67 |
8 |
|
T68 |
1 |
| others[1] |
230 |
1 |
|
T38 |
1 |
|
T386 |
1 |
|
T67 |
10 |
| others[2] |
208 |
1 |
|
T31 |
1 |
|
T62 |
1 |
|
T67 |
5 |
| others[3] |
357 |
1 |
|
T17 |
1 |
|
T320 |
1 |
|
T134 |
1 |
| false |
113 |
1 |
|
T62 |
1 |
|
T30 |
1 |
|
T97 |
1 |
| true |
5820 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1295 |
1 |
|
T37 |
1 |
|
T62 |
1 |
|
T34 |
5 |
| others[1] |
1220 |
1 |
|
T30 |
1 |
|
T34 |
6 |
|
T66 |
1 |
| others[2] |
1271 |
1 |
|
T4 |
1 |
|
T34 |
2 |
|
T95 |
1 |
| others[3] |
2052 |
1 |
|
T3 |
1 |
|
T14 |
1 |
|
T16 |
1 |
| false |
648 |
1 |
|
T32 |
1 |
|
T34 |
3 |
|
T35 |
1 |
| true |
449 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1264 |
1 |
|
T14 |
1 |
|
T95 |
1 |
|
T103 |
1 |
| others[1] |
1224 |
1 |
|
T15 |
1 |
|
T53 |
1 |
|
T34 |
3 |
| others[2] |
1289 |
1 |
|
T37 |
1 |
|
T62 |
1 |
|
T34 |
7 |
| others[3] |
2078 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T20 |
1 |
| false |
651 |
1 |
|
T4 |
1 |
|
T34 |
2 |
|
T185 |
1 |
| true |
429 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
102 |
1 |
|
T62 |
2 |
|
T67 |
4 |
|
T225 |
1 |
| others[1] |
115 |
1 |
|
T386 |
2 |
|
T58 |
1 |
|
T67 |
3 |
| others[2] |
94 |
1 |
|
T58 |
1 |
|
T67 |
2 |
|
T91 |
1 |
| others[3] |
164 |
1 |
|
T58 |
2 |
|
T67 |
3 |
|
T89 |
1 |
| false |
52 |
1 |
|
T67 |
1 |
|
T89 |
1 |
|
T388 |
1 |
| true |
6408 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
249 |
1 |
|
T57 |
1 |
|
T386 |
2 |
|
T58 |
1 |
| others[1] |
260 |
1 |
|
T15 |
1 |
|
T62 |
1 |
|
T21 |
1 |
| others[2] |
241 |
1 |
|
T31 |
1 |
|
T62 |
1 |
|
T33 |
1 |
| others[3] |
386 |
1 |
|
T22 |
1 |
|
T58 |
1 |
|
T67 |
14 |
| false |
114 |
1 |
|
T320 |
1 |
|
T67 |
8 |
|
T99 |
5 |
| true |
5685 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1113 |
1 |
|
T16 |
1 |
|
T20 |
1 |
|
T32 |
1 |
| others[1] |
1131 |
1 |
|
T4 |
1 |
|
T62 |
1 |
|
T34 |
4 |
| others[2] |
1127 |
1 |
|
T14 |
1 |
|
T17 |
1 |
|
T53 |
1 |
| others[3] |
1639 |
1 |
|
T37 |
1 |
|
T32 |
1 |
|
T34 |
8 |
| false |
528 |
1 |
|
T3 |
1 |
|
T28 |
1 |
|
T34 |
1 |
| true |
1397 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
246 |
1 |
|
T30 |
1 |
|
T67 |
7 |
|
T277 |
1 |
| others[1] |
217 |
1 |
|
T38 |
1 |
|
T97 |
1 |
|
T67 |
13 |
| others[2] |
241 |
1 |
|
T386 |
1 |
|
T67 |
8 |
|
T99 |
11 |
| others[3] |
349 |
1 |
|
T62 |
1 |
|
T386 |
1 |
|
T58 |
1 |
| false |
135 |
1 |
|
T28 |
1 |
|
T58 |
1 |
|
T67 |
4 |
| true |
5747 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
214 |
1 |
|
T57 |
1 |
|
T320 |
1 |
|
T386 |
1 |
| others[1] |
218 |
1 |
|
T58 |
1 |
|
T134 |
1 |
|
T67 |
10 |
| others[2] |
228 |
1 |
|
T2 |
1 |
|
T38 |
1 |
|
T62 |
1 |
| others[3] |
359 |
1 |
|
T177 |
1 |
|
T97 |
1 |
|
T67 |
16 |
| false |
112 |
1 |
|
T31 |
1 |
|
T58 |
1 |
|
T67 |
4 |
| true |
5804 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1266 |
1 |
|
T3 |
1 |
|
T30 |
1 |
|
T34 |
2 |
| others[1] |
1274 |
1 |
|
T4 |
1 |
|
T10 |
1 |
|
T62 |
2 |
| others[2] |
1232 |
1 |
|
T53 |
1 |
|
T34 |
6 |
|
T35 |
1 |
| others[3] |
2066 |
1 |
|
T14 |
1 |
|
T5 |
1 |
|
T16 |
1 |
| false |
650 |
1 |
|
T34 |
3 |
|
T66 |
2 |
|
T202 |
2 |
| true |
447 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1247 |
1 |
|
T34 |
4 |
|
T102 |
1 |
|
T126 |
1 |
| others[1] |
1248 |
1 |
|
T3 |
1 |
|
T37 |
1 |
|
T20 |
1 |
| others[2] |
1262 |
1 |
|
T53 |
1 |
|
T34 |
3 |
|
T96 |
1 |
| others[3] |
2087 |
1 |
|
T4 |
1 |
|
T14 |
1 |
|
T16 |
1 |
| false |
663 |
1 |
|
T28 |
1 |
|
T34 |
1 |
|
T95 |
1 |
| true |
428 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
108 |
1 |
|
T62 |
1 |
|
T58 |
2 |
|
T67 |
5 |
| others[1] |
108 |
1 |
|
T386 |
1 |
|
T58 |
1 |
|
T67 |
4 |
| others[2] |
103 |
1 |
|
T67 |
1 |
|
T388 |
1 |
|
T387 |
1 |
| others[3] |
180 |
1 |
|
T62 |
1 |
|
T30 |
1 |
|
T386 |
1 |
| false |
50 |
1 |
|
T67 |
1 |
|
T225 |
1 |
|
T99 |
3 |
| true |
6386 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
248 |
1 |
|
T17 |
1 |
|
T30 |
1 |
|
T67 |
6 |
| others[1] |
215 |
1 |
|
T62 |
1 |
|
T58 |
1 |
|
T67 |
6 |
| others[2] |
255 |
1 |
|
T2 |
1 |
|
T62 |
1 |
|
T33 |
1 |
| others[3] |
404 |
1 |
|
T38 |
1 |
|
T31 |
1 |
|
T28 |
1 |
| false |
127 |
1 |
|
T15 |
1 |
|
T57 |
1 |
|
T67 |
2 |
| true |
5686 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1107 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T16 |
1 |
| others[1] |
1064 |
1 |
|
T17 |
1 |
|
T20 |
1 |
|
T28 |
1 |
| others[2] |
1034 |
1 |
|
T1 |
1 |
|
T53 |
1 |
|
T34 |
1 |
| others[3] |
1853 |
1 |
|
T3 |
1 |
|
T14 |
1 |
|
T37 |
1 |
| false |
569 |
1 |
|
T32 |
1 |
|
T34 |
2 |
|
T35 |
1 |
| true |
1308 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T38 |
1 |
|
T21 |
1 |
|
T67 |
13 |
| others[1] |
246 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T28 |
1 |
| others[2] |
218 |
1 |
|
T67 |
11 |
|
T89 |
1 |
|
T277 |
1 |
| others[3] |
364 |
1 |
|
T62 |
2 |
|
T30 |
1 |
|
T67 |
18 |
| false |
113 |
1 |
|
T31 |
1 |
|
T57 |
1 |
|
T67 |
5 |
| true |
5774 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
219 |
1 |
|
T62 |
1 |
|
T320 |
1 |
|
T67 |
15 |
| others[1] |
204 |
1 |
|
T67 |
11 |
|
T136 |
1 |
|
T99 |
13 |
| others[2] |
224 |
1 |
|
T30 |
1 |
|
T67 |
9 |
|
T99 |
8 |
| others[3] |
367 |
1 |
|
T2 |
1 |
|
T31 |
1 |
|
T58 |
2 |
| false |
95 |
1 |
|
T38 |
1 |
|
T386 |
1 |
|
T67 |
6 |
| true |
5826 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1278 |
1 |
|
T30 |
1 |
|
T34 |
3 |
|
T96 |
1 |
| others[1] |
1247 |
1 |
|
T3 |
1 |
|
T20 |
1 |
|
T62 |
1 |
| others[2] |
1211 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T34 |
3 |
| others[3] |
2077 |
1 |
|
T4 |
1 |
|
T14 |
1 |
|
T53 |
1 |
| false |
690 |
1 |
|
T37 |
1 |
|
T34 |
1 |
|
T102 |
1 |
| true |
432 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T15 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |