Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1262 |
1 |
|
T4 |
1 |
|
T34 |
2 |
|
T102 |
1 |
| others[1] |
1263 |
1 |
|
T14 |
1 |
|
T53 |
1 |
|
T37 |
1 |
| others[2] |
1225 |
1 |
|
T62 |
2 |
|
T30 |
1 |
|
T34 |
6 |
| others[3] |
2104 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T10 |
1 |
| false |
658 |
1 |
|
T34 |
1 |
|
T66 |
5 |
|
T202 |
6 |
| true |
423 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
91 |
1 |
|
T177 |
1 |
|
T67 |
3 |
|
T387 |
1 |
| others[1] |
114 |
1 |
|
T386 |
1 |
|
T67 |
9 |
|
T89 |
1 |
| others[2] |
98 |
1 |
|
T38 |
1 |
|
T62 |
2 |
|
T67 |
4 |
| others[3] |
176 |
1 |
|
T58 |
4 |
|
T67 |
5 |
|
T388 |
1 |
| false |
63 |
1 |
|
T386 |
1 |
|
T67 |
1 |
|
T388 |
1 |
| true |
6393 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
259 |
1 |
|
T15 |
1 |
|
T58 |
1 |
|
T67 |
16 |
| others[1] |
227 |
1 |
|
T17 |
1 |
|
T19 |
1 |
|
T177 |
1 |
| others[2] |
230 |
1 |
|
T2 |
1 |
|
T31 |
1 |
|
T62 |
1 |
| others[3] |
392 |
1 |
|
T38 |
1 |
|
T21 |
1 |
|
T67 |
15 |
| false |
115 |
1 |
|
T386 |
1 |
|
T67 |
3 |
|
T99 |
1 |
| true |
5712 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1068 |
1 |
|
T53 |
1 |
|
T62 |
1 |
|
T30 |
1 |
| others[1] |
1105 |
1 |
|
T16 |
1 |
|
T62 |
1 |
|
T34 |
3 |
| others[2] |
1078 |
1 |
|
T2 |
1 |
|
T37 |
1 |
|
T19 |
1 |
| others[3] |
1739 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T14 |
1 |
| false |
558 |
1 |
|
T177 |
1 |
|
T34 |
2 |
|
T35 |
1 |
| true |
1387 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T320 |
1 |
|
T386 |
1 |
|
T67 |
17 |
| others[1] |
218 |
1 |
|
T31 |
1 |
|
T177 |
1 |
|
T57 |
1 |
| others[2] |
238 |
1 |
|
T386 |
1 |
|
T67 |
6 |
|
T99 |
6 |
| others[3] |
381 |
1 |
|
T2 |
1 |
|
T38 |
1 |
|
T67 |
19 |
| false |
129 |
1 |
|
T15 |
1 |
|
T67 |
2 |
|
T387 |
1 |
| true |
5728 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
248 |
1 |
|
T67 |
7 |
|
T387 |
1 |
|
T99 |
8 |
| others[1] |
226 |
1 |
|
T38 |
1 |
|
T386 |
1 |
|
T134 |
1 |
| others[2] |
215 |
1 |
|
T62 |
1 |
|
T58 |
1 |
|
T67 |
8 |
| others[3] |
371 |
1 |
|
T17 |
1 |
|
T62 |
1 |
|
T30 |
1 |
| false |
86 |
1 |
|
T67 |
3 |
|
T99 |
6 |
|
T391 |
1 |
| true |
5789 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1229 |
1 |
|
T34 |
3 |
|
T35 |
1 |
|
T66 |
5 |
| others[1] |
1270 |
1 |
|
T20 |
1 |
|
T34 |
3 |
|
T103 |
1 |
| others[2] |
1273 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T62 |
2 |
| others[3] |
2107 |
1 |
|
T2 |
1 |
|
T14 |
1 |
|
T53 |
1 |
| false |
615 |
1 |
|
T4 |
1 |
|
T106 |
1 |
|
T66 |
2 |
| true |
441 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1290 |
1 |
|
T3 |
1 |
|
T53 |
1 |
|
T37 |
1 |
| others[1] |
1289 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T34 |
3 |
| others[2] |
1275 |
1 |
|
T20 |
1 |
|
T34 |
3 |
|
T103 |
1 |
| others[3] |
2020 |
1 |
|
T4 |
1 |
|
T62 |
1 |
|
T30 |
1 |
| false |
635 |
1 |
|
T34 |
2 |
|
T102 |
1 |
|
T35 |
1 |
| true |
426 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
96 |
1 |
|
T67 |
8 |
|
T91 |
1 |
|
T69 |
5 |
| others[1] |
90 |
1 |
|
T58 |
1 |
|
T67 |
3 |
|
T68 |
1 |
| others[2] |
90 |
1 |
|
T386 |
1 |
|
T67 |
3 |
|
T388 |
1 |
| others[3] |
187 |
1 |
|
T62 |
1 |
|
T30 |
1 |
|
T58 |
3 |
| false |
52 |
1 |
|
T62 |
1 |
|
T386 |
1 |
|
T67 |
2 |
| true |
6420 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
248 |
1 |
|
T67 |
12 |
|
T68 |
1 |
|
T99 |
8 |
| others[1] |
238 |
1 |
|
T31 |
1 |
|
T62 |
1 |
|
T58 |
2 |
| others[2] |
244 |
1 |
|
T28 |
1 |
|
T67 |
6 |
|
T388 |
1 |
| others[3] |
398 |
1 |
|
T30 |
1 |
|
T21 |
1 |
|
T204 |
1 |
| false |
111 |
1 |
|
T320 |
1 |
|
T134 |
1 |
|
T67 |
6 |
| true |
5696 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1037 |
1 |
|
T5 |
1 |
|
T34 |
3 |
|
T35 |
1 |
| others[1] |
1085 |
1 |
|
T14 |
1 |
|
T37 |
1 |
|
T19 |
1 |
| others[2] |
1090 |
1 |
|
T16 |
1 |
|
T17 |
1 |
|
T62 |
1 |
| others[3] |
1787 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T53 |
1 |
| false |
535 |
1 |
|
T10 |
1 |
|
T34 |
1 |
|
T95 |
1 |
| true |
1401 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
215 |
1 |
|
T57 |
1 |
|
T67 |
6 |
|
T99 |
14 |
| others[1] |
228 |
1 |
|
T320 |
1 |
|
T67 |
11 |
|
T136 |
1 |
| others[2] |
222 |
1 |
|
T58 |
1 |
|
T67 |
5 |
|
T277 |
1 |
| others[3] |
398 |
1 |
|
T15 |
1 |
|
T386 |
1 |
|
T97 |
1 |
| false |
122 |
1 |
|
T177 |
1 |
|
T58 |
1 |
|
T67 |
5 |
| true |
5750 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T67 |
10 |
|
T89 |
1 |
|
T99 |
10 |
| others[1] |
226 |
1 |
|
T17 |
1 |
|
T30 |
1 |
|
T67 |
10 |
| others[2] |
224 |
1 |
|
T58 |
1 |
|
T67 |
12 |
|
T91 |
1 |
| others[3] |
334 |
1 |
|
T38 |
1 |
|
T62 |
1 |
|
T58 |
1 |
| false |
95 |
1 |
|
T2 |
1 |
|
T67 |
3 |
|
T99 |
3 |
| true |
5832 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1282 |
1 |
|
T16 |
1 |
|
T17 |
1 |
|
T53 |
1 |
| others[1] |
1259 |
1 |
|
T37 |
1 |
|
T30 |
1 |
|
T34 |
7 |
| others[2] |
1254 |
1 |
|
T62 |
1 |
|
T34 |
2 |
|
T102 |
1 |
| others[3] |
2079 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T14 |
1 |
| false |
611 |
1 |
|
T34 |
1 |
|
T66 |
3 |
|
T23 |
1 |
| true |
450 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1235 |
1 |
|
T53 |
1 |
|
T30 |
1 |
|
T34 |
3 |
| others[1] |
1234 |
1 |
|
T3 |
1 |
|
T37 |
1 |
|
T62 |
1 |
| others[2] |
1299 |
1 |
|
T16 |
1 |
|
T62 |
1 |
|
T34 |
7 |
| others[3] |
2091 |
1 |
|
T4 |
1 |
|
T14 |
1 |
|
T20 |
1 |
| false |
654 |
1 |
|
T66 |
2 |
|
T58 |
3 |
|
T202 |
2 |
| true |
422 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
113 |
1 |
|
T30 |
1 |
|
T58 |
1 |
|
T67 |
6 |
| others[1] |
91 |
1 |
|
T58 |
1 |
|
T67 |
4 |
|
T99 |
2 |
| others[2] |
102 |
1 |
|
T62 |
1 |
|
T58 |
1 |
|
T67 |
1 |
| others[3] |
190 |
1 |
|
T62 |
1 |
|
T386 |
2 |
|
T58 |
1 |
| false |
54 |
1 |
|
T67 |
1 |
|
T388 |
1 |
|
T387 |
1 |
| true |
6385 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
236 |
1 |
|
T17 |
1 |
|
T62 |
1 |
|
T21 |
1 |
| others[1] |
243 |
1 |
|
T33 |
1 |
|
T58 |
1 |
|
T134 |
1 |
| others[2] |
236 |
1 |
|
T15 |
1 |
|
T31 |
1 |
|
T67 |
8 |
| others[3] |
396 |
1 |
|
T57 |
1 |
|
T386 |
1 |
|
T58 |
2 |
| false |
126 |
1 |
|
T62 |
1 |
|
T320 |
1 |
|
T67 |
5 |
| true |
5698 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1042 |
1 |
|
T31 |
1 |
|
T34 |
6 |
|
T95 |
1 |
| others[1] |
1066 |
1 |
|
T4 |
1 |
|
T30 |
1 |
|
T34 |
6 |
| others[2] |
1081 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T20 |
1 |
| others[3] |
1806 |
1 |
|
T3 |
1 |
|
T14 |
1 |
|
T15 |
1 |
| false |
540 |
1 |
|
T53 |
1 |
|
T19 |
1 |
|
T62 |
1 |
| true |
1400 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
209 |
1 |
|
T2 |
1 |
|
T38 |
1 |
|
T58 |
1 |
| others[1] |
257 |
1 |
|
T62 |
1 |
|
T28 |
1 |
|
T67 |
8 |
| others[2] |
209 |
1 |
|
T67 |
12 |
|
T68 |
1 |
|
T387 |
1 |
| others[3] |
396 |
1 |
|
T177 |
1 |
|
T386 |
1 |
|
T58 |
1 |
| false |
110 |
1 |
|
T62 |
1 |
|
T320 |
1 |
|
T58 |
1 |
| true |
5754 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
212 |
1 |
|
T177 |
1 |
|
T58 |
2 |
|
T67 |
8 |
| others[1] |
216 |
1 |
|
T67 |
9 |
|
T91 |
1 |
|
T388 |
1 |
| others[2] |
217 |
1 |
|
T38 |
1 |
|
T62 |
1 |
|
T67 |
9 |
| others[3] |
388 |
1 |
|
T2 |
1 |
|
T62 |
1 |
|
T67 |
13 |
| false |
106 |
1 |
|
T386 |
1 |
|
T67 |
5 |
|
T387 |
1 |
| true |
5796 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1275 |
1 |
|
T3 |
1 |
|
T20 |
1 |
|
T34 |
2 |
| others[1] |
1265 |
1 |
|
T37 |
1 |
|
T34 |
4 |
|
T35 |
1 |
| others[2] |
1227 |
1 |
|
T4 |
1 |
|
T14 |
1 |
|
T62 |
1 |
| others[3] |
2055 |
1 |
|
T16 |
1 |
|
T53 |
1 |
|
T62 |
1 |
| false |
670 |
1 |
|
T34 |
4 |
|
T96 |
1 |
|
T66 |
1 |
| true |
443 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1216 |
1 |
|
T53 |
1 |
|
T62 |
1 |
|
T32 |
1 |
| others[1] |
1288 |
1 |
|
T34 |
6 |
|
T103 |
1 |
|
T106 |
1 |
| others[2] |
1267 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T20 |
1 |
| others[3] |
2099 |
1 |
|
T14 |
1 |
|
T62 |
1 |
|
T30 |
1 |
| false |
637 |
1 |
|
T4 |
1 |
|
T37 |
1 |
|
T34 |
3 |
| true |
428 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
101 |
1 |
|
T62 |
1 |
|
T67 |
3 |
|
T388 |
1 |
| others[1] |
119 |
1 |
|
T177 |
1 |
|
T386 |
1 |
|
T67 |
2 |
| others[2] |
103 |
1 |
|
T17 |
1 |
|
T67 |
7 |
|
T91 |
1 |
| others[3] |
188 |
1 |
|
T62 |
1 |
|
T386 |
1 |
|
T58 |
1 |
| false |
54 |
1 |
|
T30 |
1 |
|
T58 |
3 |
|
T67 |
1 |
| true |
6370 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
219 |
1 |
|
T204 |
1 |
|
T67 |
11 |
|
T89 |
1 |
| others[1] |
260 |
1 |
|
T28 |
1 |
|
T22 |
1 |
|
T58 |
2 |
| others[2] |
236 |
1 |
|
T19 |
1 |
|
T386 |
1 |
|
T58 |
1 |
| others[3] |
424 |
1 |
|
T57 |
1 |
|
T386 |
1 |
|
T134 |
1 |
| false |
125 |
1 |
|
T31 |
1 |
|
T67 |
3 |
|
T99 |
3 |
| true |
5671 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1044 |
1 |
|
T5 |
1 |
|
T38 |
1 |
|
T34 |
1 |
| others[1] |
1084 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T53 |
1 |
| others[2] |
1084 |
1 |
|
T3 |
1 |
|
T14 |
1 |
|
T37 |
1 |
| others[3] |
1778 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T15 |
1 |
| false |
569 |
1 |
|
T34 |
4 |
|
T146 |
1 |
|
T102 |
1 |
| true |
1376 |
1 |
|
T17 |
1 |
|
T10 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
230 |
1 |
|
T28 |
1 |
|
T21 |
1 |
|
T320 |
1 |
| others[1] |
207 |
1 |
|
T67 |
9 |
|
T91 |
1 |
|
T99 |
10 |
| others[2] |
228 |
1 |
|
T62 |
1 |
|
T177 |
1 |
|
T67 |
7 |
| others[3] |
385 |
1 |
|
T15 |
1 |
|
T62 |
1 |
|
T58 |
2 |
| false |
114 |
1 |
|
T67 |
7 |
|
T89 |
1 |
|
T99 |
5 |
| true |
5771 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
214 |
1 |
|
T17 |
1 |
|
T67 |
10 |
|
T99 |
12 |
| others[1] |
191 |
1 |
|
T58 |
1 |
|
T67 |
9 |
|
T48 |
1 |
| others[2] |
225 |
1 |
|
T62 |
1 |
|
T67 |
11 |
|
T388 |
1 |
| others[3] |
379 |
1 |
|
T30 |
1 |
|
T67 |
14 |
|
T89 |
1 |
| false |
134 |
1 |
|
T67 |
7 |
|
T390 |
1 |
|
T99 |
5 |
| true |
5792 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1287 |
1 |
|
T16 |
1 |
|
T20 |
1 |
|
T34 |
7 |
| others[1] |
1301 |
1 |
|
T14 |
1 |
|
T37 |
1 |
|
T34 |
3 |
| others[2] |
1199 |
1 |
|
T17 |
1 |
|
T62 |
2 |
|
T34 |
3 |
| others[3] |
2064 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T32 |
1 |
| false |
638 |
1 |
|
T53 |
1 |
|
T34 |
2 |
|
T35 |
1 |
| true |
446 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8 |
1 |
|
T105 |
1 |
|
T169 |
1 |
|
T170 |
1 |
| others[1] |
16 |
1 |
|
T39 |
1 |
|
T143 |
1 |
|
T393 |
1 |
| others[2] |
7 |
1 |
|
T123 |
1 |
|
T168 |
1 |
|
T72 |
2 |
| others[3] |
9 |
1 |
|
T156 |
1 |
|
T394 |
1 |
|
T395 |
1 |
| false |
6 |
1 |
|
T5 |
1 |
|
T396 |
1 |
|
T397 |
1 |
| true |
52 |
1 |
|
T9 |
1 |
|
T70 |
1 |
|
T123 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2 |
1 |
|
T182 |
1 |
|
T398 |
1 |
|
- |
- |
| others[1] |
6 |
1 |
|
T399 |
1 |
|
T400 |
1 |
|
T401 |
1 |
| others[2] |
2 |
1 |
|
T402 |
1 |
|
T403 |
1 |
|
- |
- |
| others[3] |
2 |
1 |
|
T404 |
1 |
|
T405 |
1 |
|
- |
- |
| false |
10 |
1 |
|
T319 |
1 |
|
T406 |
1 |
|
T407 |
1 |
| true |
25 |
1 |
|
T25 |
1 |
|
T26 |
1 |
|
T27 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1 |
1 |
|
T408 |
1 |
|
- |
- |
|
- |
- |
| others[1] |
3 |
1 |
|
T25 |
1 |
|
T409 |
1 |
|
T410 |
1 |
| others[2] |
4 |
1 |
|
T26 |
1 |
|
T411 |
1 |
|
T412 |
1 |
| others[3] |
1 |
1 |
|
T413 |
1 |
|
- |
- |
|
- |
- |
| false |
10 |
1 |
|
T414 |
1 |
|
T181 |
1 |
|
T399 |
1 |
| true |
28 |
1 |
|
T27 |
1 |
|
T319 |
1 |
|
T406 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |