Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10845 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T40 |
149 |
| others[1] |
750 |
1 |
|
T4 |
1 |
|
T53 |
1 |
|
T34 |
4 |
| others[2] |
834 |
1 |
|
T30 |
1 |
|
T34 |
4 |
|
T96 |
1 |
| others[3] |
1350 |
1 |
|
T37 |
1 |
|
T20 |
1 |
|
T62 |
1 |
| false |
476 |
1 |
|
T14 |
1 |
|
T34 |
2 |
|
T66 |
1 |
| true |
519 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2577 |
1 |
|
T4 |
1 |
|
T40 |
28 |
|
T38 |
1 |
| others[1] |
2534 |
1 |
|
T16 |
1 |
|
T40 |
28 |
|
T34 |
5 |
| others[2] |
2523 |
1 |
|
T2 |
1 |
|
T14 |
1 |
|
T53 |
1 |
| others[3] |
4202 |
1 |
|
T17 |
1 |
|
T40 |
44 |
|
T31 |
1 |
| false |
1347 |
1 |
|
T3 |
1 |
|
T37 |
1 |
|
T40 |
11 |
| true |
1591 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10322 |
1 |
|
T40 |
149 |
|
T56 |
2 |
|
T35 |
1 |
| others[1] |
273 |
1 |
|
T14 |
1 |
|
T37 |
1 |
|
T177 |
1 |
| others[2] |
272 |
1 |
|
T57 |
1 |
|
T33 |
1 |
|
T96 |
1 |
| others[3] |
479 |
1 |
|
T53 |
1 |
|
T38 |
1 |
|
T62 |
1 |
| false |
152 |
1 |
|
T95 |
1 |
|
T97 |
1 |
|
T67 |
7 |
| true |
3276 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10518 |
1 |
|
T40 |
149 |
|
T19 |
1 |
|
T56 |
2 |
| others[1] |
470 |
1 |
|
T28 |
1 |
|
T177 |
1 |
|
T34 |
3 |
| others[2] |
448 |
1 |
|
T1 |
1 |
|
T62 |
1 |
|
T34 |
2 |
| others[3] |
843 |
1 |
|
T5 |
1 |
|
T10 |
1 |
|
T62 |
1 |
| false |
247 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T34 |
2 |
| true |
2248 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10312 |
1 |
|
T53 |
1 |
|
T40 |
149 |
|
T56 |
2 |
| others[1] |
242 |
1 |
|
T16 |
1 |
|
T185 |
1 |
|
T97 |
1 |
| others[2] |
271 |
1 |
|
T14 |
1 |
|
T17 |
1 |
|
T30 |
1 |
| others[3] |
430 |
1 |
|
T3 |
1 |
|
T57 |
1 |
|
T386 |
1 |
| false |
124 |
1 |
|
T4 |
1 |
|
T386 |
1 |
|
T58 |
1 |
| true |
3395 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10307 |
1 |
|
T40 |
149 |
|
T56 |
2 |
|
T97 |
1 |
| others[1] |
264 |
1 |
|
T30 |
1 |
|
T67 |
13 |
|
T93 |
1 |
| others[2] |
265 |
1 |
|
T20 |
1 |
|
T102 |
1 |
|
T106 |
1 |
| others[3] |
449 |
1 |
|
T3 |
1 |
|
T37 |
1 |
|
T62 |
1 |
| false |
133 |
1 |
|
T38 |
1 |
|
T35 |
1 |
|
T134 |
1 |
| true |
3356 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10867 |
1 |
|
T16 |
1 |
|
T37 |
1 |
|
T40 |
149 |
| others[1] |
799 |
1 |
|
T19 |
1 |
|
T34 |
3 |
|
T95 |
1 |
| others[2] |
829 |
1 |
|
T3 |
1 |
|
T34 |
5 |
|
T35 |
2 |
| others[3] |
1347 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T20 |
1 |
| false |
425 |
1 |
|
T14 |
1 |
|
T53 |
1 |
|
T34 |
2 |
| true |
507 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10874 |
1 |
|
T53 |
1 |
|
T40 |
149 |
|
T62 |
1 |
| others[1] |
817 |
1 |
|
T20 |
1 |
|
T62 |
1 |
|
T34 |
5 |
| others[2] |
798 |
1 |
|
T15 |
1 |
|
T37 |
1 |
|
T34 |
4 |
| others[3] |
1288 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T14 |
1 |
| false |
437 |
1 |
|
T34 |
1 |
|
T96 |
1 |
|
T35 |
1 |
| true |
537 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2537 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T14 |
1 |
| others[1] |
2527 |
1 |
|
T37 |
1 |
|
T40 |
20 |
|
T34 |
3 |
| others[2] |
2529 |
1 |
|
T40 |
42 |
|
T31 |
1 |
|
T20 |
1 |
| others[3] |
4244 |
1 |
|
T40 |
43 |
|
T38 |
1 |
|
T62 |
1 |
| false |
1352 |
1 |
|
T40 |
15 |
|
T62 |
1 |
|
T34 |
2 |
| true |
1562 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10314 |
1 |
|
T53 |
1 |
|
T40 |
149 |
|
T19 |
1 |
| others[1] |
295 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T22 |
1 |
| others[2] |
269 |
1 |
|
T2 |
1 |
|
T28 |
1 |
|
T96 |
1 |
| others[3] |
437 |
1 |
|
T15 |
1 |
|
T31 |
1 |
|
T177 |
1 |
| false |
149 |
1 |
|
T23 |
1 |
|
T204 |
1 |
|
T67 |
6 |
| true |
3287 |
1 |
|
T1 |
1 |
|
T14 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10542 |
1 |
|
T16 |
1 |
|
T40 |
149 |
|
T56 |
2 |
| others[1] |
492 |
1 |
|
T15 |
1 |
|
T10 |
1 |
|
T38 |
1 |
| others[2] |
466 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T5 |
1 |
| others[3] |
830 |
1 |
|
T3 |
1 |
|
T19 |
1 |
|
T62 |
1 |
| false |
218 |
1 |
|
T33 |
1 |
|
T35 |
1 |
|
T66 |
1 |
| true |
2203 |
1 |
|
T2 |
1 |
|
T14 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10321 |
1 |
|
T2 |
1 |
|
T40 |
149 |
|
T56 |
2 |
| others[1] |
261 |
1 |
|
T35 |
1 |
|
T185 |
1 |
|
T58 |
1 |
| others[2] |
233 |
1 |
|
T62 |
1 |
|
T30 |
1 |
|
T106 |
1 |
| others[3] |
450 |
1 |
|
T16 |
1 |
|
T53 |
1 |
|
T386 |
2 |
| false |
142 |
1 |
|
T37 |
1 |
|
T95 |
1 |
|
T67 |
4 |
| true |
3344 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10290 |
1 |
|
T40 |
149 |
|
T62 |
1 |
|
T56 |
2 |
| others[1] |
248 |
1 |
|
T3 |
1 |
|
T14 |
1 |
|
T53 |
1 |
| others[2] |
258 |
1 |
|
T386 |
1 |
|
T58 |
1 |
|
T67 |
13 |
| others[3] |
442 |
1 |
|
T37 |
1 |
|
T38 |
1 |
|
T31 |
1 |
| false |
148 |
1 |
|
T2 |
1 |
|
T96 |
1 |
|
T58 |
1 |
| true |
3365 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10849 |
1 |
|
T3 |
1 |
|
T14 |
1 |
|
T40 |
149 |
| others[1] |
796 |
1 |
|
T16 |
1 |
|
T37 |
1 |
|
T20 |
1 |
| others[2] |
833 |
1 |
|
T5 |
1 |
|
T53 |
1 |
|
T62 |
1 |
| others[3] |
1371 |
1 |
|
T4 |
1 |
|
T15 |
1 |
|
T32 |
1 |
| false |
408 |
1 |
|
T34 |
4 |
|
T95 |
1 |
|
T102 |
1 |
| true |
494 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10839 |
1 |
|
T40 |
149 |
|
T62 |
1 |
|
T56 |
2 |
| others[1] |
822 |
1 |
|
T14 |
1 |
|
T53 |
1 |
|
T34 |
6 |
| others[2] |
795 |
1 |
|
T16 |
1 |
|
T37 |
1 |
|
T62 |
1 |
| others[3] |
1350 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T30 |
1 |
| false |
416 |
1 |
|
T3 |
1 |
|
T19 |
1 |
|
T35 |
1 |
| true |
529 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2504 |
1 |
|
T53 |
1 |
|
T37 |
1 |
|
T40 |
23 |
| others[1] |
2597 |
1 |
|
T17 |
1 |
|
T40 |
30 |
|
T20 |
1 |
| others[2] |
2497 |
1 |
|
T40 |
41 |
|
T56 |
1 |
|
T30 |
1 |
| others[3] |
4261 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T14 |
1 |
| false |
1321 |
1 |
|
T40 |
10 |
|
T62 |
1 |
|
T34 |
2 |
| true |
1571 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10322 |
1 |
|
T4 |
1 |
|
T40 |
149 |
|
T31 |
1 |
| others[1] |
282 |
1 |
|
T17 |
1 |
|
T20 |
1 |
|
T57 |
1 |
| others[2] |
280 |
1 |
|
T95 |
1 |
|
T386 |
1 |
|
T58 |
1 |
| others[3] |
448 |
1 |
|
T38 |
1 |
|
T62 |
1 |
|
T177 |
1 |
| false |
139 |
1 |
|
T67 |
6 |
|
T99 |
4 |
|
T137 |
1 |
| true |
3280 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10579 |
1 |
|
T1 |
1 |
|
T14 |
1 |
|
T37 |
1 |
| others[1] |
452 |
1 |
|
T10 |
1 |
|
T34 |
1 |
|
T35 |
1 |
| others[2] |
435 |
1 |
|
T5 |
1 |
|
T19 |
1 |
|
T28 |
1 |
| others[3] |
848 |
1 |
|
T2 |
1 |
|
T62 |
1 |
|
T32 |
1 |
| false |
244 |
1 |
|
T17 |
1 |
|
T20 |
1 |
|
T34 |
1 |
| true |
2193 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10337 |
1 |
|
T14 |
1 |
|
T40 |
149 |
|
T38 |
1 |
| others[1] |
248 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T35 |
1 |
| others[2] |
258 |
1 |
|
T37 |
1 |
|
T57 |
1 |
|
T103 |
1 |
| others[3] |
398 |
1 |
|
T16 |
1 |
|
T67 |
14 |
|
T48 |
1 |
| false |
145 |
1 |
|
T30 |
1 |
|
T67 |
8 |
|
T205 |
1 |
| true |
3365 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10309 |
1 |
|
T4 |
1 |
|
T40 |
149 |
|
T20 |
1 |
| others[1] |
242 |
1 |
|
T14 |
1 |
|
T67 |
12 |
|
T388 |
1 |
| others[2] |
269 |
1 |
|
T2 |
1 |
|
T62 |
1 |
|
T30 |
1 |
| others[3] |
402 |
1 |
|
T53 |
1 |
|
T37 |
1 |
|
T57 |
1 |
| false |
130 |
1 |
|
T386 |
1 |
|
T58 |
1 |
|
T67 |
6 |
| true |
3399 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10886 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T40 |
149 |
| others[1] |
785 |
1 |
|
T37 |
1 |
|
T34 |
3 |
|
T95 |
1 |
| others[2] |
843 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T34 |
3 |
| others[3] |
1316 |
1 |
|
T14 |
1 |
|
T17 |
1 |
|
T53 |
1 |
| false |
424 |
1 |
|
T34 |
4 |
|
T66 |
3 |
|
T58 |
1 |
| true |
497 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10859 |
1 |
|
T40 |
149 |
|
T56 |
2 |
|
T34 |
3 |
| others[1] |
787 |
1 |
|
T19 |
1 |
|
T34 |
5 |
|
T106 |
1 |
| others[2] |
805 |
1 |
|
T20 |
1 |
|
T30 |
1 |
|
T34 |
6 |
| others[3] |
1325 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T14 |
1 |
| false |
435 |
1 |
|
T53 |
1 |
|
T34 |
1 |
|
T95 |
1 |
| true |
540 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2552 |
1 |
|
T40 |
36 |
|
T56 |
1 |
|
T34 |
6 |
| others[1] |
2492 |
1 |
|
T3 |
1 |
|
T40 |
29 |
|
T34 |
4 |
| others[2] |
2561 |
1 |
|
T4 |
1 |
|
T14 |
1 |
|
T16 |
1 |
| others[3] |
4276 |
1 |
|
T53 |
1 |
|
T37 |
1 |
|
T40 |
41 |
| false |
1319 |
1 |
|
T40 |
18 |
|
T56 |
1 |
|
T34 |
2 |
| true |
1551 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10346 |
1 |
|
T4 |
1 |
|
T40 |
149 |
|
T31 |
1 |
| others[1] |
258 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T62 |
1 |
| others[2] |
297 |
1 |
|
T19 |
1 |
|
T28 |
1 |
|
T33 |
1 |
| others[3] |
425 |
1 |
|
T15 |
1 |
|
T30 |
1 |
|
T177 |
1 |
| false |
133 |
1 |
|
T35 |
1 |
|
T58 |
1 |
|
T67 |
6 |
| true |
3292 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10550 |
1 |
|
T40 |
149 |
|
T56 |
2 |
|
T34 |
3 |
| others[1] |
501 |
1 |
|
T4 |
1 |
|
T30 |
1 |
|
T34 |
2 |
| others[2] |
437 |
1 |
|
T14 |
1 |
|
T10 |
1 |
|
T32 |
1 |
| others[3] |
778 |
1 |
|
T1 |
1 |
|
T53 |
1 |
|
T19 |
1 |
| false |
243 |
1 |
|
T34 |
2 |
|
T66 |
1 |
|
T202 |
1 |
| true |
2242 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10316 |
1 |
|
T16 |
1 |
|
T17 |
1 |
|
T53 |
1 |
| others[1] |
273 |
1 |
|
T2 |
1 |
|
T102 |
1 |
|
T185 |
1 |
| others[2] |
295 |
1 |
|
T20 |
1 |
|
T177 |
1 |
|
T21 |
1 |
| others[3] |
399 |
1 |
|
T37 |
1 |
|
T38 |
1 |
|
T106 |
1 |
| false |
134 |
1 |
|
T15 |
1 |
|
T67 |
5 |
|
T91 |
1 |
| true |
3334 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10302 |
1 |
|
T4 |
1 |
|
T40 |
149 |
|
T38 |
1 |
| others[1] |
257 |
1 |
|
T16 |
1 |
|
T35 |
1 |
|
T58 |
1 |
| others[2] |
269 |
1 |
|
T31 |
1 |
|
T177 |
1 |
|
T106 |
1 |
| others[3] |
421 |
1 |
|
T3 |
1 |
|
T57 |
1 |
|
T102 |
1 |
| false |
119 |
1 |
|
T30 |
1 |
|
T134 |
1 |
|
T67 |
3 |
| true |
3383 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10836 |
1 |
|
T16 |
1 |
|
T40 |
149 |
|
T56 |
2 |
| others[1] |
817 |
1 |
|
T53 |
1 |
|
T30 |
1 |
|
T34 |
3 |
| others[2] |
806 |
1 |
|
T4 |
1 |
|
T32 |
1 |
|
T34 |
5 |
| others[3] |
1373 |
1 |
|
T3 |
1 |
|
T14 |
1 |
|
T37 |
1 |
| false |
414 |
1 |
|
T62 |
1 |
|
T34 |
1 |
|
T185 |
1 |
| true |
505 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10867 |
1 |
|
T53 |
1 |
|
T40 |
149 |
|
T20 |
1 |
| others[1] |
802 |
1 |
|
T62 |
1 |
|
T34 |
1 |
|
T95 |
1 |
| others[2] |
794 |
1 |
|
T30 |
1 |
|
T34 |
7 |
|
T126 |
1 |
| others[3] |
1293 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T14 |
1 |
| false |
459 |
1 |
|
T37 |
1 |
|
T66 |
1 |
|
T58 |
1 |
| true |
536 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2564 |
1 |
|
T17 |
1 |
|
T53 |
1 |
|
T40 |
30 |
| others[1] |
2516 |
1 |
|
T4 |
1 |
|
T40 |
27 |
|
T34 |
6 |
| others[2] |
2555 |
1 |
|
T3 |
1 |
|
T14 |
1 |
|
T40 |
28 |
| others[3] |
4199 |
1 |
|
T16 |
1 |
|
T37 |
1 |
|
T40 |
49 |
| false |
1357 |
1 |
|
T40 |
15 |
|
T56 |
1 |
|
T34 |
1 |
| true |
1560 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10353 |
1 |
|
T40 |
149 |
|
T20 |
1 |
|
T56 |
2 |
| others[1] |
277 |
1 |
|
T58 |
2 |
|
T67 |
13 |
|
T48 |
1 |
| others[2] |
246 |
1 |
|
T31 |
1 |
|
T62 |
1 |
|
T177 |
1 |
| others[3] |
465 |
1 |
|
T2 |
1 |
|
T14 |
1 |
|
T15 |
1 |
| false |
152 |
1 |
|
T4 |
1 |
|
T53 |
1 |
|
T35 |
1 |
| true |
3258 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |