Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10544 |
1 |
|
T53 |
1 |
|
T40 |
149 |
|
T62 |
1 |
| others[1] |
473 |
1 |
|
T3 |
1 |
|
T62 |
1 |
|
T35 |
1 |
| others[2] |
482 |
1 |
|
T5 |
1 |
|
T10 |
1 |
|
T34 |
3 |
| others[3] |
779 |
1 |
|
T4 |
1 |
|
T14 |
1 |
|
T15 |
1 |
| false |
235 |
1 |
|
T38 |
1 |
|
T35 |
1 |
|
T66 |
2 |
| true |
2238 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10298 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T40 |
149 |
| others[1] |
247 |
1 |
|
T14 |
1 |
|
T95 |
1 |
|
T35 |
1 |
| others[2] |
287 |
1 |
|
T30 |
1 |
|
T58 |
1 |
|
T67 |
11 |
| others[3] |
416 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T37 |
1 |
| false |
149 |
1 |
|
T103 |
1 |
|
T67 |
3 |
|
T88 |
1 |
| true |
3354 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10291 |
1 |
|
T2 |
1 |
|
T37 |
1 |
|
T40 |
149 |
| others[1] |
261 |
1 |
|
T31 |
1 |
|
T20 |
1 |
|
T57 |
1 |
| others[2] |
260 |
1 |
|
T38 |
1 |
|
T30 |
1 |
|
T103 |
1 |
| others[3] |
405 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T62 |
1 |
| false |
148 |
1 |
|
T58 |
1 |
|
T67 |
11 |
|
T99 |
9 |
| true |
3386 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10846 |
1 |
|
T3 |
1 |
|
T40 |
149 |
|
T20 |
1 |
| others[1] |
816 |
1 |
|
T62 |
1 |
|
T34 |
2 |
|
T102 |
1 |
| others[2] |
798 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T62 |
1 |
| others[3] |
1337 |
1 |
|
T14 |
1 |
|
T53 |
1 |
|
T37 |
1 |
| false |
448 |
1 |
|
T30 |
1 |
|
T34 |
5 |
|
T103 |
1 |
| true |
506 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10860 |
1 |
|
T40 |
149 |
|
T56 |
2 |
|
T34 |
6 |
| others[1] |
825 |
1 |
|
T20 |
1 |
|
T62 |
1 |
|
T34 |
4 |
| others[2] |
794 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T30 |
1 |
| others[3] |
1318 |
1 |
|
T4 |
1 |
|
T14 |
1 |
|
T34 |
6 |
| false |
430 |
1 |
|
T53 |
1 |
|
T37 |
1 |
|
T35 |
1 |
| true |
524 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2599 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T40 |
26 |
| others[1] |
2449 |
1 |
|
T4 |
1 |
|
T53 |
1 |
|
T40 |
29 |
| others[2] |
2649 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T40 |
30 |
| others[3] |
4175 |
1 |
|
T37 |
1 |
|
T40 |
44 |
|
T38 |
1 |
| false |
1296 |
1 |
|
T40 |
20 |
|
T62 |
1 |
|
T56 |
1 |
| true |
1583 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10323 |
1 |
|
T40 |
149 |
|
T56 |
2 |
|
T22 |
1 |
| others[1] |
275 |
1 |
|
T14 |
1 |
|
T15 |
1 |
|
T62 |
1 |
| others[2] |
276 |
1 |
|
T53 |
1 |
|
T95 |
1 |
|
T97 |
1 |
| others[3] |
436 |
1 |
|
T2 |
1 |
|
T62 |
1 |
|
T177 |
1 |
| false |
141 |
1 |
|
T35 |
3 |
|
T67 |
3 |
|
T304 |
1 |
| true |
3300 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10534 |
1 |
|
T15 |
1 |
|
T40 |
149 |
|
T10 |
1 |
| others[1] |
469 |
1 |
|
T19 |
1 |
|
T20 |
1 |
|
T146 |
1 |
| others[2] |
452 |
1 |
|
T62 |
1 |
|
T34 |
6 |
|
T95 |
1 |
| others[3] |
793 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T16 |
1 |
| false |
240 |
1 |
|
T34 |
1 |
|
T22 |
1 |
|
T386 |
1 |
| true |
2263 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10323 |
1 |
|
T40 |
149 |
|
T56 |
2 |
|
T95 |
1 |
| others[1] |
279 |
1 |
|
T31 |
1 |
|
T30 |
1 |
|
T103 |
1 |
| others[2] |
280 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T14 |
1 |
| others[3] |
416 |
1 |
|
T62 |
1 |
|
T35 |
2 |
|
T58 |
1 |
| false |
116 |
1 |
|
T67 |
5 |
|
T89 |
1 |
|
T200 |
1 |
| true |
3337 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10306 |
1 |
|
T53 |
1 |
|
T40 |
149 |
|
T56 |
2 |
| others[1] |
268 |
1 |
|
T20 |
1 |
|
T35 |
1 |
|
T134 |
1 |
| others[2] |
269 |
1 |
|
T4 |
1 |
|
T386 |
1 |
|
T67 |
10 |
| others[3] |
421 |
1 |
|
T16 |
1 |
|
T62 |
1 |
|
T177 |
1 |
| false |
128 |
1 |
|
T2 |
1 |
|
T67 |
5 |
|
T304 |
1 |
| true |
3359 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10895 |
1 |
|
T16 |
1 |
|
T53 |
1 |
|
T40 |
149 |
| others[1] |
804 |
1 |
|
T2 |
1 |
|
T62 |
1 |
|
T34 |
3 |
| others[2] |
839 |
1 |
|
T3 |
1 |
|
T14 |
1 |
|
T17 |
1 |
| others[3] |
1297 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T62 |
1 |
| false |
408 |
1 |
|
T32 |
1 |
|
T34 |
3 |
|
T103 |
1 |
| true |
508 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10863 |
1 |
|
T40 |
149 |
|
T56 |
2 |
|
T30 |
1 |
| others[1] |
809 |
1 |
|
T3 |
1 |
|
T14 |
1 |
|
T53 |
1 |
| others[2] |
848 |
1 |
|
T15 |
1 |
|
T16 |
1 |
|
T37 |
1 |
| others[3] |
1311 |
1 |
|
T4 |
1 |
|
T28 |
1 |
|
T34 |
6 |
| false |
412 |
1 |
|
T62 |
1 |
|
T32 |
1 |
|
T34 |
1 |
| true |
508 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2615 |
1 |
|
T16 |
1 |
|
T53 |
1 |
|
T40 |
26 |
| others[1] |
2531 |
1 |
|
T2 |
1 |
|
T40 |
28 |
|
T38 |
1 |
| others[2] |
2495 |
1 |
|
T40 |
34 |
|
T56 |
2 |
|
T34 |
7 |
| others[3] |
4241 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T14 |
1 |
| false |
1305 |
1 |
|
T40 |
13 |
|
T34 |
3 |
|
T66 |
2 |
| true |
1564 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10334 |
1 |
|
T16 |
1 |
|
T40 |
149 |
|
T56 |
2 |
| others[1] |
278 |
1 |
|
T17 |
1 |
|
T38 |
1 |
|
T177 |
1 |
| others[2] |
272 |
1 |
|
T28 |
1 |
|
T22 |
1 |
|
T204 |
1 |
| others[3] |
452 |
1 |
|
T2 |
1 |
|
T31 |
1 |
|
T62 |
1 |
| false |
141 |
1 |
|
T67 |
6 |
|
T225 |
1 |
|
T99 |
6 |
| true |
3274 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10535 |
1 |
|
T17 |
1 |
|
T40 |
149 |
|
T38 |
1 |
| others[1] |
470 |
1 |
|
T14 |
1 |
|
T37 |
1 |
|
T19 |
1 |
| others[2] |
467 |
1 |
|
T34 |
1 |
|
T95 |
1 |
|
T96 |
1 |
| others[3] |
753 |
1 |
|
T62 |
1 |
|
T34 |
4 |
|
T57 |
1 |
| false |
264 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T62 |
1 |
| true |
2262 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10308 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T40 |
149 |
| others[1] |
268 |
1 |
|
T37 |
1 |
|
T31 |
1 |
|
T20 |
1 |
| others[2] |
247 |
1 |
|
T320 |
1 |
|
T67 |
6 |
|
T225 |
1 |
| others[3] |
430 |
1 |
|
T103 |
1 |
|
T58 |
2 |
|
T67 |
18 |
| false |
164 |
1 |
|
T386 |
1 |
|
T67 |
11 |
|
T415 |
1 |
| true |
3334 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10317 |
1 |
|
T2 |
1 |
|
T37 |
1 |
|
T40 |
149 |
| others[1] |
234 |
1 |
|
T103 |
1 |
|
T58 |
1 |
|
T97 |
1 |
| others[2] |
238 |
1 |
|
T57 |
1 |
|
T67 |
8 |
|
T99 |
4 |
| others[3] |
436 |
1 |
|
T17 |
1 |
|
T62 |
1 |
|
T95 |
1 |
| false |
139 |
1 |
|
T38 |
1 |
|
T177 |
1 |
|
T106 |
1 |
| true |
3387 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10811 |
1 |
|
T3 |
1 |
|
T53 |
1 |
|
T40 |
149 |
| others[1] |
842 |
1 |
|
T4 |
1 |
|
T34 |
2 |
|
T95 |
1 |
| others[2] |
815 |
1 |
|
T14 |
1 |
|
T30 |
1 |
|
T34 |
4 |
| others[3] |
1374 |
1 |
|
T16 |
1 |
|
T17 |
1 |
|
T20 |
1 |
| false |
408 |
1 |
|
T37 |
1 |
|
T34 |
3 |
|
T66 |
1 |
| true |
501 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10855 |
1 |
|
T3 |
1 |
|
T40 |
149 |
|
T20 |
1 |
| others[1] |
786 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T37 |
1 |
| others[2] |
776 |
1 |
|
T14 |
1 |
|
T15 |
1 |
|
T53 |
1 |
| others[3] |
1364 |
1 |
|
T30 |
1 |
|
T34 |
8 |
|
T96 |
1 |
| false |
434 |
1 |
|
T34 |
4 |
|
T66 |
3 |
|
T202 |
1 |
| true |
536 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2514 |
1 |
|
T16 |
1 |
|
T40 |
36 |
|
T31 |
1 |
| others[1] |
2536 |
1 |
|
T14 |
1 |
|
T53 |
1 |
|
T40 |
28 |
| others[2] |
2568 |
1 |
|
T3 |
1 |
|
T40 |
26 |
|
T56 |
1 |
| others[3] |
4276 |
1 |
|
T4 |
1 |
|
T37 |
1 |
|
T40 |
41 |
| false |
1299 |
1 |
|
T40 |
18 |
|
T34 |
3 |
|
T35 |
1 |
| true |
1558 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10326 |
1 |
|
T40 |
149 |
|
T56 |
2 |
|
T30 |
1 |
| others[1] |
289 |
1 |
|
T3 |
1 |
|
T53 |
1 |
|
T38 |
1 |
| others[2] |
264 |
1 |
|
T17 |
1 |
|
T103 |
1 |
|
T97 |
1 |
| others[3] |
479 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T37 |
1 |
| false |
138 |
1 |
|
T67 |
4 |
|
T48 |
1 |
|
T213 |
1 |
| true |
3255 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10550 |
1 |
|
T3 |
1 |
|
T40 |
149 |
|
T56 |
2 |
| others[1] |
449 |
1 |
|
T17 |
1 |
|
T62 |
1 |
|
T30 |
1 |
| others[2] |
476 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T5 |
1 |
| others[3] |
789 |
1 |
|
T53 |
1 |
|
T31 |
1 |
|
T20 |
1 |
| false |
245 |
1 |
|
T15 |
1 |
|
T34 |
2 |
|
T35 |
1 |
| true |
2242 |
1 |
|
T2 |
1 |
|
T14 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10318 |
1 |
|
T3 |
1 |
|
T40 |
149 |
|
T56 |
2 |
| others[1] |
268 |
1 |
|
T30 |
1 |
|
T21 |
1 |
|
T35 |
1 |
| others[2] |
246 |
1 |
|
T16 |
1 |
|
T20 |
1 |
|
T62 |
1 |
| others[3] |
451 |
1 |
|
T15 |
1 |
|
T17 |
1 |
|
T37 |
1 |
| false |
135 |
1 |
|
T386 |
1 |
|
T58 |
1 |
|
T67 |
5 |
| true |
3333 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10332 |
1 |
|
T3 |
1 |
|
T14 |
1 |
|
T16 |
1 |
| others[1] |
252 |
1 |
|
T38 |
1 |
|
T95 |
1 |
|
T23 |
1 |
| others[2] |
247 |
1 |
|
T67 |
2 |
|
T93 |
1 |
|
T388 |
1 |
| others[3] |
379 |
1 |
|
T53 |
1 |
|
T31 |
1 |
|
T58 |
2 |
| false |
140 |
1 |
|
T35 |
1 |
|
T67 |
5 |
|
T99 |
9 |
| true |
3401 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10862 |
1 |
|
T40 |
149 |
|
T56 |
2 |
|
T32 |
1 |
| others[1] |
804 |
1 |
|
T14 |
1 |
|
T53 |
1 |
|
T34 |
4 |
| others[2] |
799 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T16 |
1 |
| others[3] |
1353 |
1 |
|
T37 |
1 |
|
T34 |
3 |
|
T35 |
2 |
| false |
421 |
1 |
|
T34 |
3 |
|
T103 |
1 |
|
T66 |
2 |
| true |
512 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |