Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	229995	1		T2	1234		T3	381		T4	967
auto[FlashEraseBank]	252974	1		T2	1544		T3	286		T4	1115

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	266051	1		T2	1809		T3	667		T4	935
auto[FlashOpProgram]	196426	1		T2	969		T4	1147		T5	2
auto[FlashOpErase]	16492	1		T15	35		T40	220		T25	8
auto[FlashOpInvalid]	4000	1		T98	200		T209	200		T207	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	266051	1		T2	1809		T3	667		T4	935
op[FlashOpProgram]	196426	1		T2	969		T4	1147		T5	2
op[FlashOpErase]	16492	1		T15	35		T40	220		T25	8
read_erase_read	716	1		T15	10		T25	4		T30	6
read_prog_read	1264	1		T2	10		T4	6		T17	3

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	338263	1		T2	2269		T3	667		T4	1764
auto[FlashPartInfo]	140779	1		T2	491		T4	297		T5	1
auto[FlashPartInfo1]	862	1		T2	4		T4	5		T16	2
auto[FlashPartInfo2]	3065	1		T2	14		T4	16		T5	1

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	200346	1		T2	1481		T3	667		T4	925
auto[FlashPartData]	auto[FlashOpProgram]	130279	1		T2	788		T4	839		T17	403
auto[FlashPartData]	auto[FlashOpErase]	3724	1		T15	35		T30	29		T34	4
auto[FlashPartData]	auto[FlashOpInvalid]	3914	1		T98	198		T209	200		T207	192
auto[FlashPartInfo]	auto[FlashOpRead]	63182	1		T2	312		T15	11		T17	102
auto[FlashPartInfo]	auto[FlashOpProgram]	64860	1		T2	179		T4	297		T5	1
auto[FlashPartInfo]	auto[FlashOpErase]	12669	1		T40	220		T25	8		T26	10
auto[FlashPartInfo]	auto[FlashOpInvalid]	68	1		T98	2		T207	8		T418	4
auto[FlashPartInfo1]	auto[FlashOpRead]	689	1		T2	4		T4	5		T16	2
auto[FlashPartInfo1]	auto[FlashOpProgram]	163	1		T107	32		T59	32		T111	1
auto[FlashPartInfo1]	auto[FlashOpErase]	6	1		T68	1		T419	1		T111	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	4	1		T111	2		T420	2		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1834	1		T2	12		T4	5		T16	7
auto[FlashPartInfo2]	auto[FlashOpProgram]	1124	1		T2	2		T4	11		T5	1
auto[FlashPartInfo2]	auto[FlashOpErase]	93	1		T109	1		T111	1		T421	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	14	1		T111	2		T421	2		T422	2