Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.10	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	5	27	84.38

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	5	27	84.38	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31770	1		T37	4		T40	448		T19	1
auto[1]	43	1		T338	2		T339	3		T340	2
auto[2]	99	1		T341	33		T131	4		T342	2
auto[3]	275	1		T19	1		T21	1		T22	1

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	8092	1		T37	1		T40	112		T19	1
evic_idx[1]	8058	1		T37	1		T40	112		T19	1
evic_idx[2]	8026	1		T37	1		T40	112		T30	6
evic_idx[3]	8011	1		T37	1		T40	112		T30	6

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	31070	1		T40	448		T186	440		T189	272
evic_op[2]	462	1		T37	4		T19	2		T34	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	5	27	84.38	5

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[0]]	[evic_op[1]]	[auto[2]]	0	1	1
[evic_idx[0]]	[evic_op[2]]	[auto[1]]	0	1	1
[evic_idx[1] , evic_idx[2] , evic_idx[3]]	[evic_op[1]]	[auto[2]]	--	--	3

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7704	1		T40	112		T186	110		T189	68
evic_idx[0]	evic_op[1]	auto[1]	11	1		T343	11		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	93	1		T344	24		T345	23		T346	9
evic_idx[0]	evic_op[2]	auto[0]	80	1		T37	1		T181	1		T99	1
evic_idx[0]	evic_op[2]	auto[2]	21	1		T341	9		T273	6		T347	6
evic_idx[0]	evic_op[2]	auto[3]	19	1		T19	1		T100	1		T208	1
evic_idx[1]	evic_op[1]	auto[0]	7703	1		T40	112		T186	110		T189	68
evic_idx[1]	evic_op[1]	auto[1]	6	1		T348	1		T343	5		-	-
evic_idx[1]	evic_op[1]	auto[3]	60	1		T344	21		T345	17		T346	5
evic_idx[1]	evic_op[2]	auto[0]	81	1		T37	1		T19	1		T34	1
evic_idx[1]	evic_op[2]	auto[1]	2	1		T339	1		T340	1		-	-
evic_idx[1]	evic_op[2]	auto[2]	28	1		T341	14		T342	2		T273	2
evic_idx[1]	evic_op[2]	auto[3]	14	1		T349	1		T350	1		T351	1
evic_idx[2]	evic_op[1]	auto[0]	7703	1		T40	112		T186	110		T189	68
evic_idx[2]	evic_op[1]	auto[1]	11	1		T348	1		T343	10		-	-
evic_idx[2]	evic_op[1]	auto[3]	36	1		T352	3		T344	13		T345	11
evic_idx[2]	evic_op[2]	auto[0]	75	1		T37	1		T95	1		T181	1
evic_idx[2]	evic_op[2]	auto[1]	6	1		T338	1		T339	2		T340	1
evic_idx[2]	evic_op[2]	auto[2]	20	1		T341	8		T273	5		T353	3
evic_idx[2]	evic_op[2]	auto[3]	11	1		T21	1		T22	1		T33	1
evic_idx[3]	evic_op[1]	auto[0]	7704	1		T40	112		T186	110		T189	68
evic_idx[3]	evic_op[1]	auto[1]	6	1		T348	1		T343	5		-	-
evic_idx[3]	evic_op[1]	auto[3]	33	1		T352	3		T344	9		T345	13
evic_idx[3]	evic_op[2]	auto[0]	81	1		T37	1		T181	1		T99	1
evic_idx[3]	evic_op[2]	auto[1]	1	1		T338	1		-	-		-	-
evic_idx[3]	evic_op[2]	auto[2]	14	1		T341	2		T273	6		T354	1
evic_idx[3]	evic_op[2]	auto[3]	9	1		T355	1		T356	1		T357	1