Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	29461	1		T330	2628		T331	8786		T332	1713
rd_lvl[2]	42934	1		T330	1687		T331	4862		T332	1706
rd_lvl[3]	12058	1		T330	808		T332	486		T333	593
rd_lvl[4]	37471	1		T334	2087		T330	993		T215	3047
rd_lvl[5]	14356	1		T334	801		T330	815		T215	1200
rd_lvl[6]	4632	1		T270	528		T330	6		T215	32
rd_lvl[7]	13952	1		T277	1340		T270	819		T330	789
rd_lvl[8]	20553	1		T277	1008		T270	590		T330	789
rd_lvl[9]	11670	1		T270	28		T117	602		T330	1231
rd_lvl[10]	8216	1		T14	482		T28	591		T270	28
rd_lvl[11]	9051	1		T14	334		T28	532		T335	236
rd_lvl[12]	5244	1		T29	214		T336	555		T215	44
rd_lvl[13]	7461	1		T28	62		T29	641		T116	507
rd_lvl[14]	3539	1		T116	209		T337	325		T330	54
rd_lvl[15]	4354	1		T3	475		T29	50		T199	528