Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	326868	1		T1	1		T2	2		T3	1335
all_pins[1]	326868	1		T1	1		T2	2		T3	1335
all_pins[2]	326868	1		T1	1		T2	2		T3	1335
all_pins[3]	326868	1		T1	1		T2	2		T3	1335
all_pins[4]	326868	1		T1	1		T2	2		T3	1335
all_pins[5]	326868	1		T1	1		T2	2		T3	1335

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1625787	1		T1	6		T2	12		T3	6292
values[0x1]	335421	1		T3	1718		T14	1632		T20	1080
transitions[0x0=>0x1]	301219	1		T3	1334		T14	1632		T20	1080
transitions[0x1=>0x0]	301192	1		T3	1334		T14	1632		T20	1080

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	326680	1		T1	1		T2	2		T3	1335
all_pins[0]	values[0x1]	188	1		T252	4		T253	1		T254	5
all_pins[0]	transitions[0x0=>0x1]	98	1		T322	3		T323	3		T324	4
all_pins[0]	transitions[0x1=>0x0]	71	1		T252	1		T253	1		T254	1
all_pins[1]	values[0x0]	326707	1		T1	1		T2	2		T3	1335
all_pins[1]	values[0x1]	161	1		T252	5		T253	2		T254	6
all_pins[1]	transitions[0x0=>0x1]	134	1		T252	4		T253	1		T254	5
all_pins[1]	transitions[0x1=>0x0]	2778	1		T3	192		T199	320		T359	252
all_pins[2]	values[0x0]	324063	1		T1	1		T2	2		T3	1143
all_pins[2]	values[0x1]	2805	1		T3	192		T199	320		T359	252
all_pins[2]	transitions[0x0=>0x1]	46	1		T253	1		T254	2		T322	2
all_pins[2]	transitions[0x1=>0x0]	225220	1		T3	475		T14	816		T28	1185
all_pins[3]	values[0x0]	98889	1		T1	1		T2	2		T3	668
all_pins[3]	values[0x1]	227979	1		T3	667		T14	816		T28	1185
all_pins[3]	transitions[0x0=>0x1]	196704	1		T3	475		T14	816		T28	1185
all_pins[3]	transitions[0x1=>0x0]	72949	1		T3	667		T14	816		T20	1080
all_pins[4]	values[0x0]	222644	1		T1	1		T2	2		T3	476
all_pins[4]	values[0x1]	104224	1		T3	859		T14	816		T20	1080
all_pins[4]	transitions[0x0=>0x1]	104207	1		T3	859		T14	816		T20	1080
all_pins[4]	transitions[0x1=>0x0]	47	1		T322	1		T323	1		T325	3
all_pins[5]	values[0x0]	326804	1		T1	1		T2	2		T3	1335
all_pins[5]	values[0x1]	64	1		T322	1		T323	3		T325	3
all_pins[5]	transitions[0x0=>0x1]	30	1		T322	1		T323	2		T325	1
all_pins[5]	transitions[0x1=>0x0]	127	1		T252	3		T253	1		T254	4