Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
83.33 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 36 8 28 77.78


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 6 0 6 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 36 8 28 77.78 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 293 1 T252 4 T253 4 T254 7
all_values[1] 293 1 T252 4 T253 4 T254 7
all_values[2] 293 1 T252 4 T253 4 T254 7
all_values[3] 293 1 T252 4 T253 4 T254 7
all_values[4] 293 1 T252 4 T253 4 T254 7
all_values[5] 293 1 T252 4 T253 4 T254 7



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 933 1 T252 14 T253 18 T254 20
auto[1] 825 1 T252 10 T253 6 T254 22



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 587 1 T252 10 T253 13 T254 22
auto[1] 1171 1 T252 14 T253 11 T254 20



Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1035 1 T252 17 T253 15 T254 30
auto[1] 723 1 T252 7 T253 9 T254 12



Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 36 8 28 77.78 8
Automatically Generated Cross Bins 36 8 28 77.78 8
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBER
[all_values[0] , all_values[1]] [auto[0]] * [auto[0]] -- -- 4
[all_values[2] , all_values[3]] [auto[0]] * [auto[1]] -- -- 4


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[1] 76 1 T252 1 T253 1 T254 1
all_values[0] auto[0] auto[1] auto[1] 83 1 T252 2 T254 2 T322 2
all_values[0] auto[1] auto[0] auto[1] 62 1 T252 1 T253 2 T254 2
all_values[0] auto[1] auto[1] auto[1] 72 1 T253 1 T254 2 T323 2
all_values[1] auto[0] auto[0] auto[1] 92 1 T252 1 T253 1 T254 1
all_values[1] auto[0] auto[1] auto[1] 80 1 T252 2 T254 4 T322 1
all_values[1] auto[1] auto[0] auto[1] 71 1 T253 2 T254 1 T322 1
all_values[1] auto[1] auto[1] auto[1] 50 1 T252 1 T253 1 T254 1
all_values[2] auto[0] auto[0] auto[0] 96 1 T252 1 T253 2 T254 2
all_values[2] auto[0] auto[1] auto[0] 71 1 T252 1 T254 2 T323 2
all_values[2] auto[1] auto[0] auto[1] 71 1 T252 1 T253 2 T254 2
all_values[2] auto[1] auto[1] auto[1] 55 1 T252 1 T254 1 T322 1
all_values[3] auto[0] auto[0] auto[0] 83 1 T252 1 T253 1 T254 3
all_values[3] auto[0] auto[1] auto[0] 90 1 T252 1 T253 2 T254 1
all_values[3] auto[1] auto[0] auto[1] 69 1 T252 1 T253 1 T254 3
all_values[3] auto[1] auto[1] auto[1] 51 1 T252 1 T322 2 T323 1
all_values[4] auto[0] auto[0] auto[0] 69 1 T252 2 T253 3 T254 2
all_values[4] auto[0] auto[0] auto[1] 24 1 T324 1 T325 1 T326 1
all_values[4] auto[0] auto[1] auto[0] 58 1 T253 1 T254 5 T322 1
all_values[4] auto[0] auto[1] auto[1] 34 1 T252 1 T322 1 T323 2
all_values[4] auto[1] auto[0] auto[1] 56 1 T252 1 T322 2 T323 1
all_values[4] auto[1] auto[1] auto[1] 52 1 T322 1 T323 2 T325 1
all_values[5] auto[0] auto[0] auto[0] 67 1 T252 4 T253 3 T254 3
all_values[5] auto[0] auto[0] auto[1] 35 1 T322 1 T327 1 T328 2
all_values[5] auto[0] auto[1] auto[0] 53 1 T253 1 T254 4 T322 1
all_values[5] auto[0] auto[1] auto[1] 24 1 T323 2 T325 1 T329 1
all_values[5] auto[1] auto[0] auto[1] 62 1 T322 2 T323 1 T324 1
all_values[5] auto[1] auto[1] auto[1] 52 1 T322 1 T323 1 T325 4


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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