| T1083 |
/workspace/coverage/default/0.flash_ctrl_rw.215886348 |
|
|
Apr 23 03:25:18 PM PDT 24 |
Apr 23 03:33:18 PM PDT 24 |
3768158900 ps |
| T1084 |
/workspace/coverage/default/10.flash_ctrl_invalid_op.4166048717 |
|
|
Apr 23 03:34:20 PM PDT 24 |
Apr 23 03:35:42 PM PDT 24 |
990022400 ps |
| T1085 |
/workspace/coverage/default/1.flash_ctrl_hw_rma_reset.923424146 |
|
|
Apr 23 03:26:17 PM PDT 24 |
Apr 23 03:39:18 PM PDT 24 |
70133980800 ps |
| T378 |
/workspace/coverage/default/7.flash_ctrl_disable.3786346789 |
|
|
Apr 23 03:32:44 PM PDT 24 |
Apr 23 03:33:08 PM PDT 24 |
19208500 ps |
| T1086 |
/workspace/coverage/default/37.flash_ctrl_intr_rd.378317224 |
|
|
Apr 23 03:41:02 PM PDT 24 |
Apr 23 03:43:45 PM PDT 24 |
1244827400 ps |
| T1087 |
/workspace/coverage/default/77.flash_ctrl_connect.3994183831 |
|
|
Apr 23 03:42:55 PM PDT 24 |
Apr 23 03:43:09 PM PDT 24 |
170110500 ps |
| T1088 |
/workspace/coverage/default/1.flash_ctrl_intr_wr.1372131925 |
|
|
Apr 23 03:26:43 PM PDT 24 |
Apr 23 03:28:06 PM PDT 24 |
13871401200 ps |
| T1089 |
/workspace/coverage/default/2.flash_ctrl_fetch_code.1831062330 |
|
|
Apr 23 03:27:28 PM PDT 24 |
Apr 23 03:27:49 PM PDT 24 |
109186800 ps |
| T1090 |
/workspace/coverage/default/26.flash_ctrl_sec_info_access.1842137964 |
|
|
Apr 23 03:39:32 PM PDT 24 |
Apr 23 03:40:41 PM PDT 24 |
5983444200 ps |
| T1091 |
/workspace/coverage/default/23.flash_ctrl_rw_evict_all_en.1794581072 |
|
|
Apr 23 03:38:59 PM PDT 24 |
Apr 23 03:39:28 PM PDT 24 |
37226700 ps |
| T1092 |
/workspace/coverage/default/36.flash_ctrl_sec_info_access.114599501 |
|
|
Apr 23 03:40:55 PM PDT 24 |
Apr 23 03:42:03 PM PDT 24 |
2147263500 ps |
| T1093 |
/workspace/coverage/default/39.flash_ctrl_alert_test.501388037 |
|
|
Apr 23 03:41:32 PM PDT 24 |
Apr 23 03:41:46 PM PDT 24 |
130823900 ps |
| T1094 |
/workspace/coverage/default/40.flash_ctrl_disable.1213792667 |
|
|
Apr 23 03:41:32 PM PDT 24 |
Apr 23 03:41:53 PM PDT 24 |
40265900 ps |
| T1095 |
/workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.21269579 |
|
|
Apr 23 03:39:47 PM PDT 24 |
Apr 23 03:40:19 PM PDT 24 |
510769100 ps |
| T1096 |
/workspace/coverage/default/5.flash_ctrl_rw_evict_all_en.2436247482 |
|
|
Apr 23 03:31:19 PM PDT 24 |
Apr 23 03:31:47 PM PDT 24 |
73187300 ps |
| T167 |
/workspace/coverage/default/1.flash_ctrl_rma_err.1001621039 |
|
|
Apr 23 03:27:02 PM PDT 24 |
Apr 23 03:41:58 PM PDT 24 |
81503502400 ps |
| T1097 |
/workspace/coverage/default/33.flash_ctrl_alert_test.2358734281 |
|
|
Apr 23 03:40:32 PM PDT 24 |
Apr 23 03:40:46 PM PDT 24 |
31816500 ps |
| T1098 |
/workspace/coverage/default/3.flash_ctrl_error_prog_type.1114623823 |
|
|
Apr 23 03:28:53 PM PDT 24 |
Apr 23 04:06:26 PM PDT 24 |
807903600 ps |
| T1099 |
/workspace/coverage/default/4.flash_ctrl_derr_detect.404481727 |
|
|
Apr 23 03:30:16 PM PDT 24 |
Apr 23 03:31:58 PM PDT 24 |
133254900 ps |
| T42 |
/workspace/coverage/default/1.flash_ctrl_access_after_disable.3211453677 |
|
|
Apr 23 03:26:55 PM PDT 24 |
Apr 23 03:27:09 PM PDT 24 |
148422800 ps |
| T1100 |
/workspace/coverage/default/38.flash_ctrl_sec_info_access.2605083254 |
|
|
Apr 23 03:41:17 PM PDT 24 |
Apr 23 03:42:19 PM PDT 24 |
2019997300 ps |
| T1101 |
/workspace/coverage/default/1.flash_ctrl_alert_test.2721443231 |
|
|
Apr 23 03:27:11 PM PDT 24 |
Apr 23 03:27:26 PM PDT 24 |
387415300 ps |
| T1102 |
/workspace/coverage/default/18.flash_ctrl_re_evict.3273214566 |
|
|
Apr 23 03:37:43 PM PDT 24 |
Apr 23 03:38:18 PM PDT 24 |
80810100 ps |
| T1103 |
/workspace/coverage/default/11.flash_ctrl_otp_reset.1009797053 |
|
|
Apr 23 03:34:51 PM PDT 24 |
Apr 23 03:37:03 PM PDT 24 |
201787400 ps |
| T1104 |
/workspace/coverage/default/11.flash_ctrl_mp_regions.3362099294 |
|
|
Apr 23 03:34:50 PM PDT 24 |
Apr 23 03:38:28 PM PDT 24 |
20347275900 ps |
| T1105 |
/workspace/coverage/default/6.flash_ctrl_phy_arb.235841300 |
|
|
Apr 23 03:31:28 PM PDT 24 |
Apr 23 03:41:01 PM PDT 24 |
1398366100 ps |
| T1106 |
/workspace/coverage/default/1.flash_ctrl_fs_sup.3882768040 |
|
|
Apr 23 03:26:57 PM PDT 24 |
Apr 23 03:27:32 PM PDT 24 |
264411200 ps |
| T1107 |
/workspace/coverage/default/78.flash_ctrl_connect.219157868 |
|
|
Apr 23 03:42:54 PM PDT 24 |
Apr 23 03:43:10 PM PDT 24 |
15099300 ps |
| T1108 |
/workspace/coverage/default/18.flash_ctrl_disable.2160712191 |
|
|
Apr 23 03:37:44 PM PDT 24 |
Apr 23 03:38:05 PM PDT 24 |
40402800 ps |
| T1109 |
/workspace/coverage/default/13.flash_ctrl_hw_read_seed_err.2248729803 |
|
|
Apr 23 03:35:55 PM PDT 24 |
Apr 23 03:36:09 PM PDT 24 |
15285100 ps |
| T1110 |
/workspace/coverage/default/9.flash_ctrl_rw_evict.3994609387 |
|
|
Apr 23 03:34:03 PM PDT 24 |
Apr 23 03:34:35 PM PDT 24 |
102563400 ps |
| T1111 |
/workspace/coverage/default/1.flash_ctrl_hw_read_seed_err.2784262106 |
|
|
Apr 23 03:27:08 PM PDT 24 |
Apr 23 03:27:23 PM PDT 24 |
48001500 ps |
| T1112 |
/workspace/coverage/default/16.flash_ctrl_re_evict.3484005296 |
|
|
Apr 23 03:37:08 PM PDT 24 |
Apr 23 03:37:41 PM PDT 24 |
283010900 ps |
| T1113 |
/workspace/coverage/default/9.flash_ctrl_invalid_op.2616091851 |
|
|
Apr 23 03:33:46 PM PDT 24 |
Apr 23 03:35:11 PM PDT 24 |
27169094900 ps |
| T1114 |
/workspace/coverage/default/25.flash_ctrl_connect.2481196114 |
|
|
Apr 23 03:39:25 PM PDT 24 |
Apr 23 03:39:42 PM PDT 24 |
103635500 ps |
| T1115 |
/workspace/coverage/default/14.flash_ctrl_mp_regions.756763309 |
|
|
Apr 23 03:36:05 PM PDT 24 |
Apr 23 03:56:35 PM PDT 24 |
62749390600 ps |
| T1116 |
/workspace/coverage/default/55.flash_ctrl_otp_reset.1942736778 |
|
|
Apr 23 03:42:24 PM PDT 24 |
Apr 23 03:44:37 PM PDT 24 |
71561300 ps |
| T1117 |
/workspace/coverage/default/16.flash_ctrl_sec_info_access.1984381906 |
|
|
Apr 23 03:37:08 PM PDT 24 |
Apr 23 03:38:09 PM PDT 24 |
518581100 ps |
| T1118 |
/workspace/coverage/default/4.flash_ctrl_smoke_hw.2105005419 |
|
|
Apr 23 03:29:39 PM PDT 24 |
Apr 23 03:30:02 PM PDT 24 |
40815300 ps |
| T1119 |
/workspace/coverage/default/24.flash_ctrl_smoke.3258459473 |
|
|
Apr 23 03:39:04 PM PDT 24 |
Apr 23 03:41:28 PM PDT 24 |
33572700 ps |
| T1120 |
/workspace/coverage/default/11.flash_ctrl_rand_ops.2768106433 |
|
|
Apr 23 03:34:47 PM PDT 24 |
Apr 23 03:40:32 PM PDT 24 |
98695000 ps |
| T1121 |
/workspace/coverage/default/24.flash_ctrl_otp_reset.1819543063 |
|
|
Apr 23 03:39:04 PM PDT 24 |
Apr 23 03:41:15 PM PDT 24 |
705905700 ps |
| T1122 |
/workspace/coverage/default/2.flash_ctrl_invalid_op.439196811 |
|
|
Apr 23 03:27:38 PM PDT 24 |
Apr 23 03:29:06 PM PDT 24 |
1246305700 ps |
| T1123 |
/workspace/coverage/default/7.flash_ctrl_alert_test.371031376 |
|
|
Apr 23 03:32:59 PM PDT 24 |
Apr 23 03:33:14 PM PDT 24 |
180784400 ps |
| T1124 |
/workspace/coverage/default/37.flash_ctrl_disable.1375846403 |
|
|
Apr 23 03:41:07 PM PDT 24 |
Apr 23 03:41:28 PM PDT 24 |
96449200 ps |
| T1125 |
/workspace/coverage/default/68.flash_ctrl_connect.3751013352 |
|
|
Apr 23 03:42:41 PM PDT 24 |
Apr 23 03:42:57 PM PDT 24 |
44600400 ps |
| T1126 |
/workspace/coverage/default/15.flash_ctrl_hw_sec_otp.941617443 |
|
|
Apr 23 03:36:26 PM PDT 24 |
Apr 23 03:38:16 PM PDT 24 |
4152670000 ps |
| T1127 |
/workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.1767412369 |
|
|
Apr 23 03:31:27 PM PDT 24 |
Apr 23 03:32:55 PM PDT 24 |
10020325000 ps |
| T1128 |
/workspace/coverage/default/9.flash_ctrl_hw_sec_otp.2375627976 |
|
|
Apr 23 03:33:35 PM PDT 24 |
Apr 23 03:35:37 PM PDT 24 |
47135435300 ps |
| T1129 |
/workspace/coverage/default/1.flash_ctrl_rw_evict_all_en.3459439046 |
|
|
Apr 23 03:26:42 PM PDT 24 |
Apr 23 03:27:13 PM PDT 24 |
28559600 ps |
| T1130 |
/workspace/coverage/default/63.flash_ctrl_otp_reset.2000251351 |
|
|
Apr 23 03:42:36 PM PDT 24 |
Apr 23 03:44:48 PM PDT 24 |
89845700 ps |
| T1131 |
/workspace/coverage/default/18.flash_ctrl_intr_rd.1306648590 |
|
|
Apr 23 03:37:39 PM PDT 24 |
Apr 23 03:39:59 PM PDT 24 |
9550020500 ps |
| T1132 |
/workspace/coverage/default/0.flash_ctrl_read_word_sweep_serr.2147694186 |
|
|
Apr 23 03:25:20 PM PDT 24 |
Apr 23 03:25:43 PM PDT 24 |
34502600 ps |
| T1133 |
/workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.916150095 |
|
|
Apr 23 03:37:51 PM PDT 24 |
Apr 23 03:39:32 PM PDT 24 |
10012371400 ps |
| T1134 |
/workspace/coverage/default/64.flash_ctrl_otp_reset.466929635 |
|
|
Apr 23 03:42:34 PM PDT 24 |
Apr 23 03:44:52 PM PDT 24 |
154633700 ps |
| T1135 |
/workspace/coverage/default/38.flash_ctrl_smoke.2497188074 |
|
|
Apr 23 03:41:11 PM PDT 24 |
Apr 23 03:42:50 PM PDT 24 |
18941100 ps |
| T1136 |
/workspace/coverage/default/25.flash_ctrl_intr_rd.2377716257 |
|
|
Apr 23 03:39:19 PM PDT 24 |
Apr 23 03:42:57 PM PDT 24 |
1325391400 ps |
| T1137 |
/workspace/coverage/default/31.flash_ctrl_smoke.4015771766 |
|
|
Apr 23 03:40:13 PM PDT 24 |
Apr 23 03:41:28 PM PDT 24 |
15306200 ps |
| T1138 |
/workspace/coverage/default/39.flash_ctrl_connect.3534022233 |
|
|
Apr 23 03:41:27 PM PDT 24 |
Apr 23 03:41:43 PM PDT 24 |
17582600 ps |
| T1139 |
/workspace/coverage/default/13.flash_ctrl_intr_rd.1319809820 |
|
|
Apr 23 03:35:42 PM PDT 24 |
Apr 23 03:38:30 PM PDT 24 |
1119850100 ps |
| T1140 |
/workspace/coverage/default/19.flash_ctrl_rw_evict_all_en.460091677 |
|
|
Apr 23 03:38:12 PM PDT 24 |
Apr 23 03:38:44 PM PDT 24 |
31922700 ps |
| T1141 |
/workspace/coverage/default/32.flash_ctrl_smoke.2907003069 |
|
|
Apr 23 03:40:17 PM PDT 24 |
Apr 23 03:42:40 PM PDT 24 |
33230600 ps |
| T252 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.1904392843 |
|
|
Apr 23 01:29:26 PM PDT 24 |
Apr 23 01:29:40 PM PDT 24 |
32377400 ps |
| T1142 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.3910450753 |
|
|
Apr 23 01:28:39 PM PDT 24 |
Apr 23 01:28:53 PM PDT 24 |
91347000 ps |
| T63 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3235938156 |
|
|
Apr 23 01:29:19 PM PDT 24 |
Apr 23 01:44:24 PM PDT 24 |
1280347100 ps |
| T253 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.2481172916 |
|
|
Apr 23 01:29:29 PM PDT 24 |
Apr 23 01:29:43 PM PDT 24 |
16076200 ps |
| T254 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.1784374210 |
|
|
Apr 23 01:29:27 PM PDT 24 |
Apr 23 01:29:42 PM PDT 24 |
129342900 ps |
| T64 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.2788360265 |
|
|
Apr 23 01:29:22 PM PDT 24 |
Apr 23 01:29:39 PM PDT 24 |
455107600 ps |
| T1143 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.2267656548 |
|
|
Apr 23 01:28:45 PM PDT 24 |
Apr 23 01:28:59 PM PDT 24 |
18005100 ps |
| T191 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3367559004 |
|
|
Apr 23 01:28:44 PM PDT 24 |
Apr 23 01:29:27 PM PDT 24 |
1811832000 ps |
| T322 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.1671998234 |
|
|
Apr 23 01:29:26 PM PDT 24 |
Apr 23 01:29:40 PM PDT 24 |
25740600 ps |
| T65 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.2155157560 |
|
|
Apr 23 01:29:03 PM PDT 24 |
Apr 23 01:37:00 PM PDT 24 |
3845071700 ps |
| T219 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.4165711477 |
|
|
Apr 23 01:28:47 PM PDT 24 |
Apr 23 01:29:46 PM PDT 24 |
6749245100 ps |
| T323 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.3642503286 |
|
|
Apr 23 01:28:53 PM PDT 24 |
Apr 23 01:29:07 PM PDT 24 |
120928500 ps |
| T324 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.3924977136 |
|
|
Apr 23 01:29:28 PM PDT 24 |
Apr 23 01:29:42 PM PDT 24 |
32235200 ps |
| T192 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.1847218265 |
|
|
Apr 23 01:29:02 PM PDT 24 |
Apr 23 01:36:40 PM PDT 24 |
209184600 ps |
| T220 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.50222221 |
|
|
Apr 23 01:29:06 PM PDT 24 |
Apr 23 01:29:25 PM PDT 24 |
123934600 ps |
| T325 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.2118628283 |
|
|
Apr 23 01:28:34 PM PDT 24 |
Apr 23 01:28:48 PM PDT 24 |
24980600 ps |
| T260 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.367354815 |
|
|
Apr 23 01:28:51 PM PDT 24 |
Apr 23 01:29:39 PM PDT 24 |
76238500 ps |
| T1144 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.3494490837 |
|
|
Apr 23 01:29:11 PM PDT 24 |
Apr 23 01:29:28 PM PDT 24 |
170841400 ps |
| T1145 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.666414420 |
|
|
Apr 23 01:28:57 PM PDT 24 |
Apr 23 01:29:11 PM PDT 24 |
19539200 ps |
| T244 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1150776405 |
|
|
Apr 23 01:28:34 PM PDT 24 |
Apr 23 01:29:32 PM PDT 24 |
5344491100 ps |
| T1146 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.2870987779 |
|
|
Apr 23 01:28:49 PM PDT 24 |
Apr 23 01:29:06 PM PDT 24 |
20459000 ps |
| T321 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.2387760370 |
|
|
Apr 23 01:28:51 PM PDT 24 |
Apr 23 01:29:29 PM PDT 24 |
1522425400 ps |
| T1147 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.640232170 |
|
|
Apr 23 01:29:09 PM PDT 24 |
Apr 23 01:29:25 PM PDT 24 |
12502400 ps |
| T1148 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2895530157 |
|
|
Apr 23 01:28:47 PM PDT 24 |
Apr 23 01:29:03 PM PDT 24 |
17357100 ps |
| T1149 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.4162722606 |
|
|
Apr 23 01:29:09 PM PDT 24 |
Apr 23 01:29:23 PM PDT 24 |
16931100 ps |
| T216 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.3698475015 |
|
|
Apr 23 01:29:13 PM PDT 24 |
Apr 23 01:29:28 PM PDT 24 |
56591900 ps |
| T234 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1918213232 |
|
|
Apr 23 01:28:39 PM PDT 24 |
Apr 23 01:28:53 PM PDT 24 |
19035800 ps |
| T291 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.709335936 |
|
|
Apr 23 01:29:18 PM PDT 24 |
Apr 23 01:29:37 PM PDT 24 |
145222200 ps |
| T217 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2217699629 |
|
|
Apr 23 01:29:18 PM PDT 24 |
Apr 23 01:29:35 PM PDT 24 |
118851900 ps |
| T218 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.2120071111 |
|
|
Apr 23 01:29:08 PM PDT 24 |
Apr 23 01:29:26 PM PDT 24 |
150567200 ps |
| T228 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.2693659091 |
|
|
Apr 23 01:28:37 PM PDT 24 |
Apr 23 01:28:56 PM PDT 24 |
237786000 ps |
| T229 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.2786848109 |
|
|
Apr 23 01:28:58 PM PDT 24 |
Apr 23 01:29:16 PM PDT 24 |
52177800 ps |
| T375 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.1410818621 |
|
|
Apr 23 01:29:08 PM PDT 24 |
Apr 23 01:29:23 PM PDT 24 |
62654700 ps |
| T230 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.3762577584 |
|
|
Apr 23 01:28:53 PM PDT 24 |
Apr 23 01:29:10 PM PDT 24 |
34507700 ps |
| T231 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2982786552 |
|
|
Apr 23 01:28:55 PM PDT 24 |
Apr 23 01:29:15 PM PDT 24 |
62674000 ps |
| T1150 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.4073134766 |
|
|
Apr 23 01:29:00 PM PDT 24 |
Apr 23 01:29:16 PM PDT 24 |
46014500 ps |
| T326 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.494676370 |
|
|
Apr 23 01:29:25 PM PDT 24 |
Apr 23 01:29:40 PM PDT 24 |
30436100 ps |
| T1151 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.3164792984 |
|
|
Apr 23 01:29:11 PM PDT 24 |
Apr 23 01:29:25 PM PDT 24 |
28474100 ps |
| T327 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.203646008 |
|
|
Apr 23 01:29:24 PM PDT 24 |
Apr 23 01:29:39 PM PDT 24 |
36809700 ps |
| T328 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.1184751758 |
|
|
Apr 23 01:29:03 PM PDT 24 |
Apr 23 01:29:17 PM PDT 24 |
45746000 ps |
| T297 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1574999460 |
|
|
Apr 23 01:28:45 PM PDT 24 |
Apr 23 01:29:02 PM PDT 24 |
128974200 ps |
| T1152 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.2689370736 |
|
|
Apr 23 01:29:07 PM PDT 24 |
Apr 23 01:29:23 PM PDT 24 |
27257100 ps |
| T1153 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.1477452795 |
|
|
Apr 23 01:28:43 PM PDT 24 |
Apr 23 01:29:30 PM PDT 24 |
446781900 ps |
| T1154 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.2176401232 |
|
|
Apr 23 01:29:21 PM PDT 24 |
Apr 23 01:29:38 PM PDT 24 |
35806500 ps |
| T1155 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.174086077 |
|
|
Apr 23 01:29:22 PM PDT 24 |
Apr 23 01:29:38 PM PDT 24 |
15360900 ps |
| T232 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.267847806 |
|
|
Apr 23 01:29:02 PM PDT 24 |
Apr 23 01:29:23 PM PDT 24 |
95508100 ps |
| T1156 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.1229280272 |
|
|
Apr 23 01:28:46 PM PDT 24 |
Apr 23 01:29:00 PM PDT 24 |
44170300 ps |
| T292 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.1312615348 |
|
|
Apr 23 01:28:46 PM PDT 24 |
Apr 23 01:29:26 PM PDT 24 |
3513641800 ps |
| T1157 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.3527231337 |
|
|
Apr 23 01:28:55 PM PDT 24 |
Apr 23 01:29:09 PM PDT 24 |
16366800 ps |
| T1158 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2647830830 |
|
|
Apr 23 01:29:12 PM PDT 24 |
Apr 23 01:29:25 PM PDT 24 |
13264000 ps |
| T293 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.306336914 |
|
|
Apr 23 01:29:08 PM PDT 24 |
Apr 23 01:29:25 PM PDT 24 |
588955200 ps |
| T1159 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.2356977521 |
|
|
Apr 23 01:28:45 PM PDT 24 |
Apr 23 01:29:03 PM PDT 24 |
27963700 ps |
| T1160 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.3310408021 |
|
|
Apr 23 01:29:27 PM PDT 24 |
Apr 23 01:29:41 PM PDT 24 |
16497200 ps |
| T1161 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.1393853917 |
|
|
Apr 23 01:29:25 PM PDT 24 |
Apr 23 01:29:39 PM PDT 24 |
52861900 ps |
| T296 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.4042661247 |
|
|
Apr 23 01:29:12 PM PDT 24 |
Apr 23 01:29:30 PM PDT 24 |
64292200 ps |
| T294 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.280346584 |
|
|
Apr 23 01:28:49 PM PDT 24 |
Apr 23 01:30:08 PM PDT 24 |
3217781500 ps |
| T233 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.3644239303 |
|
|
Apr 23 01:29:06 PM PDT 24 |
Apr 23 01:29:26 PM PDT 24 |
136174800 ps |
| T249 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.2347896308 |
|
|
Apr 23 01:29:06 PM PDT 24 |
Apr 23 01:29:28 PM PDT 24 |
223210700 ps |
| T1162 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.1120607662 |
|
|
Apr 23 01:29:22 PM PDT 24 |
Apr 23 01:29:40 PM PDT 24 |
225668700 ps |
| T1163 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.1748608943 |
|
|
Apr 23 01:28:54 PM PDT 24 |
Apr 23 01:29:09 PM PDT 24 |
17037900 ps |
| T295 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2860132927 |
|
|
Apr 23 01:29:06 PM PDT 24 |
Apr 23 01:36:57 PM PDT 24 |
1436261500 ps |
| T1164 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.616979662 |
|
|
Apr 23 01:29:04 PM PDT 24 |
Apr 23 01:29:20 PM PDT 24 |
12533800 ps |
| T1165 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.4284039700 |
|
|
Apr 23 01:29:26 PM PDT 24 |
Apr 23 01:29:41 PM PDT 24 |
49639300 ps |
| T1166 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.2100303943 |
|
|
Apr 23 01:29:07 PM PDT 24 |
Apr 23 01:29:24 PM PDT 24 |
60369300 ps |
| T1167 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.1240012061 |
|
|
Apr 23 01:28:45 PM PDT 24 |
Apr 23 01:29:03 PM PDT 24 |
36127700 ps |
| T250 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1176086858 |
|
|
Apr 23 01:29:12 PM PDT 24 |
Apr 23 01:36:58 PM PDT 24 |
3747687300 ps |
| T1168 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.80337077 |
|
|
Apr 23 01:28:55 PM PDT 24 |
Apr 23 01:29:11 PM PDT 24 |
26406800 ps |
| T262 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.1668402342 |
|
|
Apr 23 01:28:53 PM PDT 24 |
Apr 23 01:29:13 PM PDT 24 |
76232800 ps |
| T269 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1693901683 |
|
|
Apr 23 01:29:07 PM PDT 24 |
Apr 23 01:36:45 PM PDT 24 |
179001200 ps |
| T1169 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2508758318 |
|
|
Apr 23 01:29:01 PM PDT 24 |
Apr 23 01:29:16 PM PDT 24 |
76271300 ps |
| T1170 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.4176164766 |
|
|
Apr 23 01:28:39 PM PDT 24 |
Apr 23 01:29:44 PM PDT 24 |
1273176700 ps |
| T1171 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.1287193299 |
|
|
Apr 23 01:28:55 PM PDT 24 |
Apr 23 01:29:09 PM PDT 24 |
12505400 ps |
| T360 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.475901256 |
|
|
Apr 23 01:28:55 PM PDT 24 |
Apr 23 01:29:11 PM PDT 24 |
64862900 ps |
| T1172 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.1733642398 |
|
|
Apr 23 01:28:51 PM PDT 24 |
Apr 23 01:29:05 PM PDT 24 |
48756600 ps |
| T259 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1169595762 |
|
|
Apr 23 01:28:43 PM PDT 24 |
Apr 23 01:29:02 PM PDT 24 |
48740000 ps |
| T1173 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.1572396771 |
|
|
Apr 23 01:29:23 PM PDT 24 |
Apr 23 01:29:36 PM PDT 24 |
16527100 ps |
| T266 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.1865202726 |
|
|
Apr 23 01:28:52 PM PDT 24 |
Apr 23 01:29:10 PM PDT 24 |
53598200 ps |
| T1174 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.466956264 |
|
|
Apr 23 01:28:52 PM PDT 24 |
Apr 23 01:29:08 PM PDT 24 |
13043100 ps |
| T298 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1830100526 |
|
|
Apr 23 01:28:45 PM PDT 24 |
Apr 23 01:29:05 PM PDT 24 |
224347500 ps |
| T263 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2873907889 |
|
|
Apr 23 01:29:24 PM PDT 24 |
Apr 23 01:29:39 PM PDT 24 |
90674300 ps |
| T1175 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2591634115 |
|
|
Apr 23 01:28:59 PM PDT 24 |
Apr 23 01:29:17 PM PDT 24 |
53805400 ps |
| T299 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.3271204935 |
|
|
Apr 23 01:29:09 PM PDT 24 |
Apr 23 01:29:28 PM PDT 24 |
582189700 ps |
| T1176 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.2190935302 |
|
|
Apr 23 01:29:27 PM PDT 24 |
Apr 23 01:29:41 PM PDT 24 |
59062400 ps |
| T268 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.723995838 |
|
|
Apr 23 01:29:10 PM PDT 24 |
Apr 23 01:29:28 PM PDT 24 |
212559800 ps |
| T329 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.341668699 |
|
|
Apr 23 01:29:26 PM PDT 24 |
Apr 23 01:29:40 PM PDT 24 |
17854900 ps |
| T1177 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.4036892543 |
|
|
Apr 23 01:29:29 PM PDT 24 |
Apr 23 01:29:43 PM PDT 24 |
47068400 ps |
| T1178 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.800207974 |
|
|
Apr 23 01:29:28 PM PDT 24 |
Apr 23 01:29:42 PM PDT 24 |
26470500 ps |
| T1179 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2229197014 |
|
|
Apr 23 01:28:40 PM PDT 24 |
Apr 23 01:28:56 PM PDT 24 |
55825000 ps |
| T1180 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1207424622 |
|
|
Apr 23 01:29:22 PM PDT 24 |
Apr 23 01:29:41 PM PDT 24 |
146819200 ps |
| T1181 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.3052972157 |
|
|
Apr 23 01:29:06 PM PDT 24 |
Apr 23 01:29:19 PM PDT 24 |
35236800 ps |
| T1182 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.646369901 |
|
|
Apr 23 01:28:49 PM PDT 24 |
Apr 23 01:29:15 PM PDT 24 |
59872200 ps |
| T1183 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.2073085323 |
|
|
Apr 23 01:28:59 PM PDT 24 |
Apr 23 01:29:15 PM PDT 24 |
174833400 ps |
| T1184 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2012447711 |
|
|
Apr 23 01:28:37 PM PDT 24 |
Apr 23 01:28:51 PM PDT 24 |
21820400 ps |
| T1185 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1928274095 |
|
|
Apr 23 01:29:12 PM PDT 24 |
Apr 23 01:29:26 PM PDT 24 |
48635000 ps |
| T265 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.631809649 |
|
|
Apr 23 01:29:07 PM PDT 24 |
Apr 23 01:29:28 PM PDT 24 |
44821000 ps |
| T257 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.3906454235 |
|
|
Apr 23 01:29:11 PM PDT 24 |
Apr 23 01:29:27 PM PDT 24 |
110521800 ps |
| T1186 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.3614833756 |
|
|
Apr 23 01:29:24 PM PDT 24 |
Apr 23 01:29:38 PM PDT 24 |
15626100 ps |
| T1187 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.2690967296 |
|
|
Apr 23 01:29:30 PM PDT 24 |
Apr 23 01:29:44 PM PDT 24 |
18285900 ps |
| T1188 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.901181381 |
|
|
Apr 23 01:29:04 PM PDT 24 |
Apr 23 01:29:20 PM PDT 24 |
20660300 ps |
| T258 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.3540819268 |
|
|
Apr 23 01:28:48 PM PDT 24 |
Apr 23 01:29:05 PM PDT 24 |
75066000 ps |
| T1189 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.1632308290 |
|
|
Apr 23 01:29:26 PM PDT 24 |
Apr 23 01:29:40 PM PDT 24 |
18489800 ps |
| T1190 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.276992244 |
|
|
Apr 23 01:28:52 PM PDT 24 |
Apr 23 01:29:10 PM PDT 24 |
100547800 ps |
| T1191 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.3682097837 |
|
|
Apr 23 01:29:11 PM PDT 24 |
Apr 23 01:29:28 PM PDT 24 |
20511800 ps |
| T1192 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.1690674289 |
|
|
Apr 23 01:29:16 PM PDT 24 |
Apr 23 01:29:31 PM PDT 24 |
28321800 ps |
| T1193 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.936735306 |
|
|
Apr 23 01:29:26 PM PDT 24 |
Apr 23 01:29:41 PM PDT 24 |
74313000 ps |
| T365 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2730659395 |
|
|
Apr 23 01:28:54 PM PDT 24 |
Apr 23 01:36:42 PM PDT 24 |
359819600 ps |
| T1194 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.4112734351 |
|
|
Apr 23 01:28:36 PM PDT 24 |
Apr 23 01:28:51 PM PDT 24 |
20427000 ps |
| T264 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.3720931323 |
|
|
Apr 23 01:29:11 PM PDT 24 |
Apr 23 01:29:29 PM PDT 24 |
39744200 ps |
| T255 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.3104003361 |
|
|
Apr 23 01:29:13 PM PDT 24 |
Apr 23 01:29:32 PM PDT 24 |
59514000 ps |
| T1195 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.4090751450 |
|
|
Apr 23 01:28:54 PM PDT 24 |
Apr 23 01:29:10 PM PDT 24 |
34865400 ps |
| T1196 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.593195600 |
|
|
Apr 23 01:29:24 PM PDT 24 |
Apr 23 01:29:43 PM PDT 24 |
82599800 ps |
| T1197 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.2847650595 |
|
|
Apr 23 01:29:06 PM PDT 24 |
Apr 23 01:29:26 PM PDT 24 |
298065600 ps |
| T1198 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.2226847461 |
|
|
Apr 23 01:29:26 PM PDT 24 |
Apr 23 01:29:40 PM PDT 24 |
15939600 ps |
| T1199 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.2396449903 |
|
|
Apr 23 01:28:37 PM PDT 24 |
Apr 23 01:28:51 PM PDT 24 |
16345500 ps |
| T369 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.2696551910 |
|
|
Apr 23 01:29:11 PM PDT 24 |
Apr 23 01:36:52 PM PDT 24 |
1328964400 ps |
| T1200 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.2878838505 |
|
|
Apr 23 01:29:14 PM PDT 24 |
Apr 23 01:29:28 PM PDT 24 |
86029800 ps |
| T1201 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3869272149 |
|
|
Apr 23 01:29:20 PM PDT 24 |
Apr 23 01:29:40 PM PDT 24 |
42931200 ps |
| T1202 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.3638516075 |
|
|
Apr 23 01:28:51 PM PDT 24 |
Apr 23 01:30:07 PM PDT 24 |
3501907400 ps |
| T1203 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.2989905077 |
|
|
Apr 23 01:29:29 PM PDT 24 |
Apr 23 01:29:43 PM PDT 24 |
17764500 ps |
| T1204 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3933795720 |
|
|
Apr 23 01:29:14 PM PDT 24 |
Apr 23 01:29:36 PM PDT 24 |
869780800 ps |
| T1205 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.1975471874 |
|
|
Apr 23 01:28:59 PM PDT 24 |
Apr 23 01:29:35 PM PDT 24 |
603708600 ps |
| T1206 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.2358647498 |
|
|
Apr 23 01:29:00 PM PDT 24 |
Apr 23 01:29:14 PM PDT 24 |
28210100 ps |
| T1207 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2120292492 |
|
|
Apr 23 01:28:40 PM PDT 24 |
Apr 23 01:28:56 PM PDT 24 |
42347300 ps |
| T1208 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.2540655144 |
|
|
Apr 23 01:29:22 PM PDT 24 |
Apr 23 01:29:36 PM PDT 24 |
54120100 ps |
| T372 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2543399197 |
|
|
Apr 23 01:28:55 PM PDT 24 |
Apr 23 01:36:43 PM PDT 24 |
184201500 ps |
| T1209 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.2691350939 |
|
|
Apr 23 01:28:48 PM PDT 24 |
Apr 23 01:29:04 PM PDT 24 |
39780500 ps |
| T1210 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1909039345 |
|
|
Apr 23 01:28:52 PM PDT 24 |
Apr 23 01:29:27 PM PDT 24 |
1129544300 ps |
| T1211 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.954343561 |
|
|
Apr 23 01:29:12 PM PDT 24 |
Apr 23 01:29:26 PM PDT 24 |
62890400 ps |
| T1212 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.3253186544 |
|
|
Apr 23 01:29:07 PM PDT 24 |
Apr 23 01:29:24 PM PDT 24 |
33043000 ps |
| T1213 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.1723953208 |
|
|
Apr 23 01:29:30 PM PDT 24 |
Apr 23 01:29:44 PM PDT 24 |
16198800 ps |
| T1214 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.2270681439 |
|
|
Apr 23 01:29:11 PM PDT 24 |
Apr 23 01:29:27 PM PDT 24 |
79077500 ps |
| T1215 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.297219118 |
|
|
Apr 23 01:29:07 PM PDT 24 |
Apr 23 01:29:23 PM PDT 24 |
11905800 ps |
| T261 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.3542337451 |
|
|
Apr 23 01:28:59 PM PDT 24 |
Apr 23 01:29:16 PM PDT 24 |
143041900 ps |
| T1216 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.2044582291 |
|
|
Apr 23 01:28:43 PM PDT 24 |
Apr 23 01:29:19 PM PDT 24 |
165230900 ps |
| T256 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.2958700186 |
|
|
Apr 23 01:28:33 PM PDT 24 |
Apr 23 01:28:52 PM PDT 24 |
249749200 ps |
| T366 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.2817114066 |
|
|
Apr 23 01:29:00 PM PDT 24 |
Apr 23 01:36:40 PM PDT 24 |
452270600 ps |
| T1217 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.2551514960 |
|
|
Apr 23 01:29:11 PM PDT 24 |
Apr 23 01:29:26 PM PDT 24 |
11087500 ps |
| T1218 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3516305225 |
|
|
Apr 23 01:28:48 PM PDT 24 |
Apr 23 01:29:05 PM PDT 24 |
33911400 ps |
| T1219 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.635991398 |
|
|
Apr 23 01:28:49 PM PDT 24 |
Apr 23 01:29:05 PM PDT 24 |
72149300 ps |
| T367 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.1007204849 |
|
|
Apr 23 01:29:14 PM PDT 24 |
Apr 23 01:41:53 PM PDT 24 |
353812800 ps |
| T1220 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.3475435845 |
|
|
Apr 23 01:29:07 PM PDT 24 |
Apr 23 01:29:23 PM PDT 24 |
70265700 ps |
| T1221 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1879161277 |
|
|
Apr 23 01:28:34 PM PDT 24 |
Apr 23 01:29:07 PM PDT 24 |
1078728400 ps |
| T1222 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.1470751131 |
|
|
Apr 23 01:29:03 PM PDT 24 |
Apr 23 01:29:17 PM PDT 24 |
15695000 ps |
| T361 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3977674777 |
|
|
Apr 23 01:28:55 PM PDT 24 |
Apr 23 01:29:12 PM PDT 24 |
36625700 ps |
| T1223 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.4099843139 |
|
|
Apr 23 01:29:14 PM PDT 24 |
Apr 23 01:29:32 PM PDT 24 |
670000200 ps |
| T368 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.4014577548 |
|
|
Apr 23 01:28:51 PM PDT 24 |
Apr 23 01:41:34 PM PDT 24 |
1288283900 ps |
| T251 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.1367762033 |
|
|
Apr 23 01:28:39 PM PDT 24 |
Apr 23 01:28:58 PM PDT 24 |
52650700 ps |
| T1224 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.684111358 |
|
|
Apr 23 01:28:52 PM PDT 24 |
Apr 23 01:29:08 PM PDT 24 |
13272900 ps |
| T1225 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.1810534721 |
|
|
Apr 23 01:29:24 PM PDT 24 |
Apr 23 01:29:38 PM PDT 24 |
26491000 ps |
| T363 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2410592165 |
|
|
Apr 23 01:29:07 PM PDT 24 |
Apr 23 01:44:15 PM PDT 24 |
2842526300 ps |
| T1226 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2555921308 |
|
|
Apr 23 01:28:34 PM PDT 24 |
Apr 23 01:28:48 PM PDT 24 |
41296400 ps |
| T300 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.1580764532 |
|
|
Apr 23 01:28:36 PM PDT 24 |
Apr 23 01:28:52 PM PDT 24 |
413175000 ps |
| T362 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.685672085 |
|
|
Apr 23 01:29:11 PM PDT 24 |
Apr 23 01:29:31 PM PDT 24 |
215455100 ps |
| T1227 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.3553621151 |
|
|
Apr 23 01:29:24 PM PDT 24 |
Apr 23 01:29:38 PM PDT 24 |
47354500 ps |
| T1228 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.1826595984 |
|
|
Apr 23 01:28:54 PM PDT 24 |
Apr 23 01:29:10 PM PDT 24 |
12127200 ps |
| T1229 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.1884136158 |
|
|
Apr 23 01:29:01 PM PDT 24 |
Apr 23 01:29:17 PM PDT 24 |
15384500 ps |
| T1230 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3463116967 |
|
|
Apr 23 01:29:11 PM PDT 24 |
Apr 23 01:29:29 PM PDT 24 |
773631400 ps |
| T267 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2492859191 |
|
|
Apr 23 01:29:07 PM PDT 24 |
Apr 23 01:29:26 PM PDT 24 |
194003600 ps |
| T1231 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.3850476283 |
|
|
Apr 23 01:28:49 PM PDT 24 |
Apr 23 01:29:09 PM PDT 24 |
141351600 ps |
| T370 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.311829961 |
|
|
Apr 23 01:29:20 PM PDT 24 |
Apr 23 01:37:05 PM PDT 24 |
790377600 ps |
| T371 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.2054029396 |
|
|
Apr 23 01:28:33 PM PDT 24 |
Apr 23 01:41:08 PM PDT 24 |
2933260800 ps |
| T1232 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.60507884 |
|
|
Apr 23 01:29:00 PM PDT 24 |
Apr 23 01:29:14 PM PDT 24 |
25631800 ps |
| T1233 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1766383430 |
|
|
Apr 23 01:29:20 PM PDT 24 |
Apr 23 01:29:37 PM PDT 24 |
46499100 ps |
| T1234 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.1290163118 |
|
|
Apr 23 01:28:45 PM PDT 24 |
Apr 23 01:29:01 PM PDT 24 |
23639600 ps |
| T1235 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.4228075484 |
|
|
Apr 23 01:28:39 PM PDT 24 |
Apr 23 01:29:58 PM PDT 24 |
9563559500 ps |
| T1236 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.3946504019 |
|
|
Apr 23 01:28:56 PM PDT 24 |
Apr 23 01:29:10 PM PDT 24 |
34199400 ps |
| T1237 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.2794455501 |
|
|
Apr 23 01:29:11 PM PDT 24 |
Apr 23 01:29:31 PM PDT 24 |
95419700 ps |
| T1238 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3743755893 |
|
|
Apr 23 01:29:32 PM PDT 24 |
Apr 23 01:29:46 PM PDT 24 |
31838000 ps |
| T1239 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.1221908231 |
|
|
Apr 23 01:29:26 PM PDT 24 |
Apr 23 01:29:40 PM PDT 24 |
15856800 ps |
| T1240 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1887254406 |
|
|
Apr 23 01:29:11 PM PDT 24 |
Apr 23 01:29:27 PM PDT 24 |
36525700 ps |
| T1241 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.2006231857 |
|
|
Apr 23 01:29:29 PM PDT 24 |
Apr 23 01:29:43 PM PDT 24 |
15617800 ps |
| T1242 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1454221778 |
|
|
Apr 23 01:29:24 PM PDT 24 |
Apr 23 01:29:42 PM PDT 24 |
27676400 ps |
| T1243 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.1658933516 |
|
|
Apr 23 01:29:08 PM PDT 24 |
Apr 23 01:29:22 PM PDT 24 |
31744100 ps |
| T1244 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.633848230 |
|
|
Apr 23 01:29:28 PM PDT 24 |
Apr 23 01:29:42 PM PDT 24 |
14494800 ps |
| T1245 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1664866314 |
|
|
Apr 23 01:29:17 PM PDT 24 |
Apr 23 01:29:35 PM PDT 24 |
268357600 ps |
| T1246 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.3974160335 |
|
|
Apr 23 01:28:46 PM PDT 24 |
Apr 23 01:29:03 PM PDT 24 |
38868600 ps |
| T301 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.4170253452 |
|
|
Apr 23 01:28:55 PM PDT 24 |
Apr 23 01:29:13 PM PDT 24 |
96686900 ps |
| T1247 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2382765362 |
|
|
Apr 23 01:28:54 PM PDT 24 |
Apr 23 01:29:10 PM PDT 24 |
167933200 ps |
| T1248 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.3950513520 |
|
|
Apr 23 01:28:52 PM PDT 24 |
Apr 23 01:29:07 PM PDT 24 |
20806100 ps |
| T235 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.2154302418 |
|
|
Apr 23 01:28:42 PM PDT 24 |
Apr 23 01:28:56 PM PDT 24 |
41825600 ps |
| T1249 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1901969248 |
|
|
Apr 23 01:28:34 PM PDT 24 |
Apr 23 01:28:48 PM PDT 24 |
65515300 ps |
| T1250 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.1539037983 |
|
|
Apr 23 01:29:12 PM PDT 24 |
Apr 23 01:29:28 PM PDT 24 |
37619500 ps |
| T1251 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.1504800492 |
|
|
Apr 23 01:29:21 PM PDT 24 |
Apr 23 01:29:35 PM PDT 24 |
15835000 ps |
| T1252 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.4029305043 |
|
|
Apr 23 01:28:36 PM PDT 24 |
Apr 23 01:28:50 PM PDT 24 |
14217700 ps |
| T1253 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.4008666833 |
|
|
Apr 23 01:29:30 PM PDT 24 |
Apr 23 01:29:44 PM PDT 24 |
31538300 ps |
| T1254 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.4274001626 |
|
|
Apr 23 01:29:28 PM PDT 24 |
Apr 23 01:29:42 PM PDT 24 |
26844900 ps |
| T1255 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.634766051 |
|
|
Apr 23 01:28:56 PM PDT 24 |
Apr 23 01:29:12 PM PDT 24 |
30613800 ps |
| T1256 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.477724229 |
|
|
Apr 23 01:29:06 PM PDT 24 |
Apr 23 01:29:22 PM PDT 24 |
141531400 ps |