Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	309958	1		T1	2		T2	1		T3	1
all_values[1]	309958	1		T1	2		T2	1		T3	1
all_values[2]	309958	1		T1	2		T2	1		T3	1
all_values[3]	309958	1		T1	2		T2	1		T3	1
all_values[4]	309958	1		T1	2		T2	1		T3	1
all_values[5]	309958	1		T1	2		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	626337	1		T1	12		T2	6		T3	6
auto[1]	1233411	1		T8	5264		T28	37728		T27	5220

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	909689	1		T1	7		T2	4		T3	4
auto[1]	950059	1		T1	5		T2	2		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	309807	1		T1	2		T2	1		T3	1
all_values[0]	auto[1]	auto[1]	151	1		T246	1		T247	1		T248	5
all_values[1]	auto[0]	auto[1]	309819	1		T1	2		T2	1		T3	1
all_values[1]	auto[1]	auto[1]	139	1		T246	6		T247	7		T320	1
all_values[2]	auto[0]	auto[0]	1624	1		T1	2		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	54	1		T246	1		T248	1		T324	2
all_values[2]	auto[1]	auto[0]	308221	1		T8	1316		T28	9432		T27	1305
all_values[2]	auto[1]	auto[1]	59	1		T246	3		T247	2		T248	1
all_values[3]	auto[0]	auto[0]	1625	1		T1	2		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	46	1		T246	2		T247	1		T248	2
all_values[3]	auto[1]	auto[0]	76806	1		T28	22		T27	1305		T24	888
all_values[3]	auto[1]	auto[1]	231481	1		T8	1316		T28	9410		T24	888
all_values[4]	auto[0]	auto[0]	1155	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	531	1		T1	1		T4	1		T5	1
all_values[4]	auto[1]	auto[0]	210496	1		T8	658		T28	8507		T27	1
all_values[4]	auto[1]	auto[1]	97776	1		T8	658		T28	925		T27	1304
all_values[5]	auto[0]	auto[0]	1546	1		T1	2		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	130	1		T7	1		T20	1		T22	4
all_values[5]	auto[1]	auto[0]	308216	1		T8	1316		T28	9432		T27	1305
all_values[5]	auto[1]	auto[1]	66	1		T246	2		T247	4		T248	2