Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
90 |
1 |
|
T4 |
3 |
|
T33 |
6 |
|
T95 |
1 |
| others[1] |
98 |
1 |
|
T4 |
3 |
|
T33 |
5 |
|
T305 |
1 |
| others[2] |
96 |
1 |
|
T4 |
8 |
|
T33 |
7 |
|
T84 |
5 |
| others[3] |
190 |
1 |
|
T4 |
6 |
|
T33 |
10 |
|
T372 |
2 |
| false |
46 |
1 |
|
T4 |
2 |
|
T33 |
1 |
|
T374 |
1 |
| true |
6181 |
1 |
|
T1 |
40 |
|
T4 |
79 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
244 |
1 |
|
T4 |
12 |
|
T5 |
1 |
|
T33 |
12 |
| others[1] |
213 |
1 |
|
T4 |
15 |
|
T27 |
1 |
|
T22 |
1 |
| others[2] |
214 |
1 |
|
T4 |
9 |
|
T7 |
1 |
|
T22 |
2 |
| others[3] |
402 |
1 |
|
T4 |
14 |
|
T28 |
1 |
|
T22 |
1 |
| false |
123 |
1 |
|
T4 |
6 |
|
T33 |
3 |
|
T208 |
1 |
| true |
5505 |
1 |
|
T1 |
40 |
|
T4 |
45 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1044 |
1 |
|
T1 |
3 |
|
T4 |
22 |
|
T40 |
4 |
| others[1] |
1073 |
1 |
|
T1 |
6 |
|
T4 |
17 |
|
T7 |
1 |
| others[2] |
1001 |
1 |
|
T1 |
8 |
|
T4 |
17 |
|
T40 |
2 |
| others[3] |
1650 |
1 |
|
T1 |
22 |
|
T4 |
35 |
|
T40 |
3 |
| false |
555 |
1 |
|
T1 |
1 |
|
T4 |
10 |
|
T5 |
1 |
| true |
1378 |
1 |
|
T20 |
1 |
|
T13 |
1 |
|
T28 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T4 |
7 |
|
T22 |
1 |
|
T33 |
12 |
| others[1] |
236 |
1 |
|
T4 |
14 |
|
T5 |
1 |
|
T22 |
1 |
| others[2] |
190 |
1 |
|
T4 |
9 |
|
T33 |
10 |
|
T377 |
1 |
| others[3] |
386 |
1 |
|
T4 |
19 |
|
T20 |
1 |
|
T22 |
1 |
| false |
123 |
1 |
|
T4 |
8 |
|
T33 |
3 |
|
T182 |
1 |
| true |
5542 |
1 |
|
T1 |
40 |
|
T4 |
44 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T4 |
9 |
|
T5 |
1 |
|
T7 |
1 |
| others[1] |
212 |
1 |
|
T4 |
7 |
|
T33 |
8 |
|
T372 |
1 |
| others[2] |
229 |
1 |
|
T4 |
10 |
|
T33 |
10 |
|
T9 |
2 |
| others[3] |
337 |
1 |
|
T4 |
20 |
|
T33 |
14 |
|
T9 |
1 |
| false |
125 |
1 |
|
T4 |
6 |
|
T33 |
5 |
|
T84 |
4 |
| true |
5570 |
1 |
|
T1 |
40 |
|
T4 |
49 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1169 |
1 |
|
T1 |
6 |
|
T4 |
22 |
|
T8 |
1 |
| others[1] |
1194 |
1 |
|
T1 |
8 |
|
T4 |
14 |
|
T7 |
1 |
| others[2] |
1198 |
1 |
|
T1 |
1 |
|
T4 |
24 |
|
T40 |
2 |
| others[3] |
2023 |
1 |
|
T1 |
21 |
|
T4 |
30 |
|
T5 |
1 |
| false |
662 |
1 |
|
T1 |
4 |
|
T4 |
11 |
|
T22 |
1 |
| true |
455 |
1 |
|
T20 |
1 |
|
T28 |
1 |
|
T27 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1228 |
1 |
|
T1 |
12 |
|
T4 |
17 |
|
T8 |
1 |
| others[1] |
1289 |
1 |
|
T1 |
11 |
|
T4 |
27 |
|
T33 |
26 |
| others[2] |
1182 |
1 |
|
T1 |
5 |
|
T4 |
18 |
|
T40 |
4 |
| others[3] |
1989 |
1 |
|
T1 |
10 |
|
T4 |
34 |
|
T5 |
1 |
| false |
588 |
1 |
|
T1 |
2 |
|
T4 |
5 |
|
T40 |
2 |
| true |
425 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
108 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T33 |
4 |
| others[1] |
109 |
1 |
|
T4 |
5 |
|
T20 |
1 |
|
T33 |
4 |
| others[2] |
98 |
1 |
|
T4 |
1 |
|
T33 |
3 |
|
T84 |
2 |
| others[3] |
171 |
1 |
|
T4 |
2 |
|
T33 |
4 |
|
T373 |
1 |
| false |
44 |
1 |
|
T4 |
6 |
|
T33 |
2 |
|
T85 |
1 |
| true |
6171 |
1 |
|
T1 |
40 |
|
T4 |
86 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T4 |
11 |
|
T33 |
10 |
|
T47 |
1 |
| others[1] |
240 |
1 |
|
T4 |
13 |
|
T5 |
1 |
|
T33 |
6 |
| others[2] |
211 |
1 |
|
T4 |
13 |
|
T20 |
1 |
|
T28 |
1 |
| others[3] |
415 |
1 |
|
T4 |
13 |
|
T7 |
1 |
|
T22 |
1 |
| false |
117 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T33 |
5 |
| true |
5502 |
1 |
|
T1 |
40 |
|
T4 |
50 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1070 |
1 |
|
T1 |
5 |
|
T4 |
22 |
|
T7 |
1 |
| others[1] |
1003 |
1 |
|
T1 |
7 |
|
T4 |
14 |
|
T8 |
1 |
| others[2] |
1061 |
1 |
|
T1 |
8 |
|
T4 |
18 |
|
T42 |
1 |
| others[3] |
1656 |
1 |
|
T1 |
19 |
|
T4 |
38 |
|
T5 |
1 |
| false |
478 |
1 |
|
T1 |
1 |
|
T4 |
9 |
|
T40 |
2 |
| true |
1433 |
1 |
|
T13 |
1 |
|
T28 |
1 |
|
T27 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
247 |
1 |
|
T4 |
15 |
|
T7 |
1 |
|
T33 |
10 |
| others[1] |
200 |
1 |
|
T4 |
8 |
|
T5 |
1 |
|
T22 |
2 |
| others[2] |
225 |
1 |
|
T4 |
7 |
|
T33 |
10 |
|
T84 |
8 |
| others[3] |
382 |
1 |
|
T4 |
17 |
|
T33 |
21 |
|
T30 |
1 |
| false |
112 |
1 |
|
T4 |
4 |
|
T33 |
8 |
|
T84 |
6 |
| true |
5535 |
1 |
|
T1 |
40 |
|
T4 |
50 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
201 |
1 |
|
T4 |
11 |
|
T22 |
1 |
|
T33 |
8 |
| others[1] |
216 |
1 |
|
T4 |
15 |
|
T5 |
1 |
|
T22 |
1 |
| others[2] |
216 |
1 |
|
T4 |
7 |
|
T22 |
2 |
|
T33 |
6 |
| others[3] |
373 |
1 |
|
T4 |
22 |
|
T7 |
1 |
|
T33 |
20 |
| false |
114 |
1 |
|
T4 |
4 |
|
T33 |
4 |
|
T84 |
10 |
| true |
5581 |
1 |
|
T1 |
40 |
|
T4 |
42 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1218 |
1 |
|
T1 |
8 |
|
T4 |
12 |
|
T42 |
1 |
| others[1] |
1219 |
1 |
|
T1 |
9 |
|
T4 |
16 |
|
T5 |
1 |
| others[2] |
1141 |
1 |
|
T1 |
8 |
|
T4 |
20 |
|
T33 |
22 |
| others[3] |
2025 |
1 |
|
T1 |
9 |
|
T4 |
45 |
|
T40 |
4 |
| false |
654 |
1 |
|
T1 |
6 |
|
T4 |
8 |
|
T8 |
1 |
| true |
444 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1208 |
1 |
|
T1 |
5 |
|
T4 |
21 |
|
T42 |
1 |
| others[1] |
1195 |
1 |
|
T1 |
13 |
|
T4 |
18 |
|
T8 |
1 |
| others[2] |
1194 |
1 |
|
T1 |
6 |
|
T4 |
21 |
|
T40 |
2 |
| others[3] |
2033 |
1 |
|
T1 |
15 |
|
T4 |
31 |
|
T5 |
1 |
| false |
647 |
1 |
|
T1 |
1 |
|
T4 |
10 |
|
T40 |
1 |
| true |
424 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
88 |
1 |
|
T4 |
4 |
|
T22 |
1 |
|
T33 |
4 |
| others[1] |
111 |
1 |
|
T4 |
4 |
|
T33 |
5 |
|
T372 |
1 |
| others[2] |
110 |
1 |
|
T4 |
5 |
|
T33 |
3 |
|
T374 |
1 |
| others[3] |
173 |
1 |
|
T4 |
10 |
|
T5 |
1 |
|
T22 |
1 |
| false |
49 |
1 |
|
T33 |
2 |
|
T373 |
1 |
|
T85 |
2 |
| true |
6170 |
1 |
|
T1 |
40 |
|
T4 |
78 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
253 |
1 |
|
T4 |
14 |
|
T28 |
1 |
|
T22 |
1 |
| others[1] |
220 |
1 |
|
T4 |
7 |
|
T27 |
1 |
|
T33 |
6 |
| others[2] |
235 |
1 |
|
T4 |
6 |
|
T33 |
15 |
|
T84 |
7 |
| others[3] |
387 |
1 |
|
T4 |
17 |
|
T22 |
2 |
|
T33 |
13 |
| false |
107 |
1 |
|
T4 |
5 |
|
T33 |
5 |
|
T377 |
1 |
| true |
5499 |
1 |
|
T1 |
40 |
|
T4 |
52 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1050 |
1 |
|
T1 |
10 |
|
T4 |
16 |
|
T20 |
1 |
| others[1] |
1033 |
1 |
|
T1 |
10 |
|
T4 |
16 |
|
T8 |
1 |
| others[2] |
1033 |
1 |
|
T1 |
6 |
|
T4 |
22 |
|
T5 |
1 |
| others[3] |
1687 |
1 |
|
T1 |
12 |
|
T4 |
34 |
|
T28 |
1 |
| false |
488 |
1 |
|
T1 |
2 |
|
T4 |
13 |
|
T40 |
1 |
| true |
1410 |
1 |
|
T7 |
1 |
|
T22 |
3 |
|
T25 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
230 |
1 |
|
T4 |
12 |
|
T33 |
9 |
|
T373 |
1 |
| others[1] |
220 |
1 |
|
T4 |
6 |
|
T7 |
1 |
|
T20 |
1 |
| others[2] |
220 |
1 |
|
T4 |
7 |
|
T33 |
5 |
|
T30 |
1 |
| others[3] |
362 |
1 |
|
T4 |
11 |
|
T22 |
1 |
|
T33 |
17 |
| false |
118 |
1 |
|
T4 |
4 |
|
T33 |
5 |
|
T24 |
1 |
| true |
5551 |
1 |
|
T1 |
40 |
|
T4 |
61 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
209 |
1 |
|
T4 |
17 |
|
T22 |
2 |
|
T33 |
10 |
| others[1] |
217 |
1 |
|
T4 |
12 |
|
T33 |
8 |
|
T374 |
1 |
| others[2] |
186 |
1 |
|
T4 |
12 |
|
T22 |
3 |
|
T33 |
11 |
| others[3] |
358 |
1 |
|
T4 |
14 |
|
T5 |
1 |
|
T7 |
1 |
| false |
110 |
1 |
|
T4 |
2 |
|
T33 |
4 |
|
T84 |
7 |
| true |
5621 |
1 |
|
T1 |
40 |
|
T4 |
44 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1202 |
1 |
|
T1 |
6 |
|
T4 |
18 |
|
T33 |
25 |
| others[1] |
1174 |
1 |
|
T1 |
8 |
|
T4 |
24 |
|
T5 |
1 |
| others[2] |
1249 |
1 |
|
T1 |
5 |
|
T4 |
11 |
|
T42 |
1 |
| others[3] |
1971 |
1 |
|
T1 |
16 |
|
T4 |
38 |
|
T8 |
1 |
| false |
644 |
1 |
|
T1 |
5 |
|
T4 |
10 |
|
T40 |
1 |
| true |
461 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1123 |
1 |
|
T1 |
8 |
|
T4 |
17 |
|
T40 |
1 |
| others[1] |
1231 |
1 |
|
T1 |
5 |
|
T4 |
29 |
|
T40 |
4 |
| others[2] |
1182 |
1 |
|
T1 |
6 |
|
T4 |
21 |
|
T5 |
1 |
| others[3] |
2076 |
1 |
|
T1 |
17 |
|
T4 |
29 |
|
T8 |
1 |
| false |
661 |
1 |
|
T1 |
4 |
|
T4 |
5 |
|
T40 |
1 |
| true |
428 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
122 |
1 |
|
T4 |
5 |
|
T33 |
5 |
|
T377 |
1 |
| others[1] |
80 |
1 |
|
T4 |
5 |
|
T33 |
1 |
|
T372 |
1 |
| others[2] |
97 |
1 |
|
T4 |
4 |
|
T33 |
3 |
|
T373 |
1 |
| others[3] |
174 |
1 |
|
T4 |
4 |
|
T5 |
1 |
|
T33 |
10 |
| false |
57 |
1 |
|
T4 |
4 |
|
T33 |
4 |
|
T84 |
2 |
| true |
6171 |
1 |
|
T1 |
40 |
|
T4 |
79 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T4 |
7 |
|
T33 |
10 |
|
T24 |
1 |
| others[1] |
244 |
1 |
|
T4 |
10 |
|
T22 |
2 |
|
T33 |
10 |
| others[2] |
244 |
1 |
|
T4 |
11 |
|
T33 |
10 |
|
T153 |
1 |
| others[3] |
350 |
1 |
|
T4 |
23 |
|
T33 |
16 |
|
T224 |
1 |
| false |
150 |
1 |
|
T4 |
7 |
|
T20 |
1 |
|
T33 |
6 |
| true |
5488 |
1 |
|
T1 |
40 |
|
T4 |
43 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
992 |
1 |
|
T1 |
11 |
|
T4 |
19 |
|
T5 |
1 |
| others[1] |
1069 |
1 |
|
T1 |
9 |
|
T4 |
20 |
|
T42 |
1 |
| others[2] |
1047 |
1 |
|
T1 |
5 |
|
T4 |
15 |
|
T7 |
1 |
| others[3] |
1719 |
1 |
|
T1 |
12 |
|
T4 |
36 |
|
T8 |
1 |
| false |
503 |
1 |
|
T1 |
3 |
|
T4 |
11 |
|
T40 |
1 |
| true |
1371 |
1 |
|
T20 |
1 |
|
T13 |
1 |
|
T28 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T4 |
6 |
|
T33 |
9 |
|
T95 |
1 |
| others[1] |
196 |
1 |
|
T4 |
7 |
|
T27 |
1 |
|
T33 |
9 |
| others[2] |
229 |
1 |
|
T4 |
10 |
|
T28 |
1 |
|
T33 |
7 |
| others[3] |
413 |
1 |
|
T4 |
14 |
|
T7 |
1 |
|
T33 |
16 |
| false |
114 |
1 |
|
T4 |
4 |
|
T5 |
1 |
|
T22 |
2 |
| true |
5524 |
1 |
|
T1 |
40 |
|
T4 |
60 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
211 |
1 |
|
T4 |
7 |
|
T5 |
1 |
|
T22 |
1 |
| others[1] |
198 |
1 |
|
T4 |
9 |
|
T22 |
1 |
|
T33 |
9 |
| others[2] |
194 |
1 |
|
T4 |
9 |
|
T20 |
1 |
|
T27 |
1 |
| others[3] |
345 |
1 |
|
T4 |
14 |
|
T33 |
19 |
|
T95 |
1 |
| false |
127 |
1 |
|
T4 |
6 |
|
T7 |
1 |
|
T22 |
1 |
| true |
5626 |
1 |
|
T1 |
40 |
|
T4 |
56 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1205 |
1 |
|
T1 |
6 |
|
T4 |
19 |
|
T40 |
1 |
| others[1] |
1245 |
1 |
|
T1 |
6 |
|
T4 |
24 |
|
T40 |
4 |
| others[2] |
1184 |
1 |
|
T1 |
9 |
|
T4 |
19 |
|
T42 |
1 |
| others[3] |
2033 |
1 |
|
T1 |
17 |
|
T4 |
30 |
|
T5 |
1 |
| false |
591 |
1 |
|
T1 |
2 |
|
T4 |
9 |
|
T33 |
11 |
| true |
443 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1178 |
1 |
|
T1 |
12 |
|
T4 |
19 |
|
T5 |
1 |
| others[1] |
1177 |
1 |
|
T1 |
11 |
|
T4 |
26 |
|
T8 |
1 |
| others[2] |
1210 |
1 |
|
T1 |
5 |
|
T4 |
18 |
|
T40 |
3 |
| others[3] |
2059 |
1 |
|
T1 |
11 |
|
T4 |
28 |
|
T40 |
5 |
| false |
658 |
1 |
|
T1 |
1 |
|
T4 |
10 |
|
T33 |
16 |
| true |
419 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
100 |
1 |
|
T4 |
6 |
|
T22 |
1 |
|
T33 |
6 |
| others[1] |
91 |
1 |
|
T4 |
3 |
|
T33 |
3 |
|
T84 |
5 |
| others[2] |
118 |
1 |
|
T4 |
5 |
|
T5 |
1 |
|
T20 |
1 |
| others[3] |
187 |
1 |
|
T4 |
4 |
|
T22 |
1 |
|
T33 |
12 |
| false |
48 |
1 |
|
T4 |
3 |
|
T33 |
5 |
|
T374 |
1 |
| true |
6157 |
1 |
|
T1 |
40 |
|
T4 |
80 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
213 |
1 |
|
T4 |
6 |
|
T22 |
2 |
|
T33 |
11 |
| others[1] |
223 |
1 |
|
T4 |
9 |
|
T7 |
1 |
|
T28 |
1 |
| others[2] |
244 |
1 |
|
T4 |
12 |
|
T27 |
1 |
|
T33 |
12 |
| others[3] |
357 |
1 |
|
T4 |
16 |
|
T22 |
1 |
|
T33 |
13 |
| false |
108 |
1 |
|
T4 |
11 |
|
T33 |
2 |
|
T84 |
5 |
| true |
5556 |
1 |
|
T1 |
40 |
|
T4 |
47 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
986 |
1 |
|
T1 |
7 |
|
T4 |
23 |
|
T13 |
1 |
| others[1] |
1044 |
1 |
|
T1 |
9 |
|
T4 |
20 |
|
T5 |
1 |
| others[2] |
1065 |
1 |
|
T1 |
10 |
|
T4 |
22 |
|
T40 |
2 |
| others[3] |
1672 |
1 |
|
T1 |
13 |
|
T4 |
30 |
|
T42 |
1 |
| false |
564 |
1 |
|
T1 |
1 |
|
T4 |
6 |
|
T40 |
1 |
| true |
1370 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T28 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |