Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T4 |
9 |
|
T22 |
1 |
|
T33 |
6 |
| others[1] |
232 |
1 |
|
T4 |
15 |
|
T7 |
1 |
|
T33 |
9 |
| others[2] |
218 |
1 |
|
T4 |
8 |
|
T33 |
7 |
|
T319 |
1 |
| others[3] |
354 |
1 |
|
T4 |
14 |
|
T5 |
1 |
|
T27 |
1 |
| false |
106 |
1 |
|
T4 |
3 |
|
T33 |
6 |
|
T84 |
2 |
| true |
5563 |
1 |
|
T1 |
40 |
|
T4 |
52 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
210 |
1 |
|
T4 |
13 |
|
T22 |
1 |
|
T33 |
7 |
| others[1] |
205 |
1 |
|
T4 |
7 |
|
T27 |
1 |
|
T33 |
12 |
| others[2] |
212 |
1 |
|
T4 |
7 |
|
T33 |
9 |
|
T31 |
1 |
| others[3] |
362 |
1 |
|
T4 |
17 |
|
T5 |
1 |
|
T7 |
1 |
| false |
113 |
1 |
|
T4 |
4 |
|
T33 |
2 |
|
T84 |
4 |
| true |
5599 |
1 |
|
T1 |
40 |
|
T4 |
53 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1198 |
1 |
|
T1 |
8 |
|
T4 |
10 |
|
T8 |
1 |
| others[1] |
1177 |
1 |
|
T1 |
6 |
|
T4 |
17 |
|
T40 |
1 |
| others[2] |
1261 |
1 |
|
T1 |
10 |
|
T4 |
24 |
|
T5 |
1 |
| others[3] |
1993 |
1 |
|
T1 |
14 |
|
T4 |
36 |
|
T40 |
5 |
| false |
623 |
1 |
|
T1 |
2 |
|
T4 |
14 |
|
T33 |
14 |
| true |
449 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1165 |
1 |
|
T1 |
6 |
|
T4 |
21 |
|
T33 |
21 |
| others[1] |
1201 |
1 |
|
T1 |
8 |
|
T4 |
15 |
|
T5 |
1 |
| others[2] |
1234 |
1 |
|
T1 |
10 |
|
T4 |
15 |
|
T40 |
2 |
| others[3] |
2055 |
1 |
|
T1 |
7 |
|
T4 |
38 |
|
T40 |
5 |
| false |
624 |
1 |
|
T1 |
9 |
|
T4 |
12 |
|
T40 |
1 |
| true |
422 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
90 |
1 |
|
T4 |
3 |
|
T33 |
3 |
|
T376 |
1 |
| others[1] |
106 |
1 |
|
T4 |
5 |
|
T33 |
3 |
|
T84 |
5 |
| others[2] |
119 |
1 |
|
T4 |
6 |
|
T5 |
1 |
|
T33 |
5 |
| others[3] |
167 |
1 |
|
T4 |
9 |
|
T33 |
8 |
|
T372 |
1 |
| false |
43 |
1 |
|
T4 |
3 |
|
T84 |
1 |
|
T85 |
1 |
| true |
6176 |
1 |
|
T1 |
40 |
|
T4 |
75 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
213 |
1 |
|
T4 |
7 |
|
T28 |
1 |
|
T33 |
12 |
| others[1] |
220 |
1 |
|
T4 |
7 |
|
T33 |
12 |
|
T31 |
1 |
| others[2] |
207 |
1 |
|
T4 |
4 |
|
T22 |
3 |
|
T33 |
7 |
| others[3] |
393 |
1 |
|
T4 |
21 |
|
T22 |
2 |
|
T33 |
19 |
| false |
112 |
1 |
|
T4 |
9 |
|
T5 |
1 |
|
T33 |
6 |
| true |
5556 |
1 |
|
T1 |
40 |
|
T4 |
53 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1046 |
1 |
|
T1 |
6 |
|
T4 |
28 |
|
T5 |
1 |
| others[1] |
1016 |
1 |
|
T1 |
9 |
|
T4 |
16 |
|
T20 |
1 |
| others[2] |
1084 |
1 |
|
T1 |
10 |
|
T4 |
22 |
|
T42 |
1 |
| others[3] |
1705 |
1 |
|
T1 |
13 |
|
T4 |
29 |
|
T8 |
1 |
| false |
478 |
1 |
|
T1 |
2 |
|
T4 |
6 |
|
T33 |
16 |
| true |
1372 |
1 |
|
T7 |
1 |
|
T13 |
1 |
|
T22 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
257 |
1 |
|
T4 |
10 |
|
T22 |
1 |
|
T33 |
10 |
| others[1] |
189 |
1 |
|
T4 |
8 |
|
T33 |
13 |
|
T84 |
7 |
| others[2] |
214 |
1 |
|
T4 |
3 |
|
T33 |
12 |
|
T95 |
1 |
| others[3] |
375 |
1 |
|
T4 |
24 |
|
T7 |
1 |
|
T28 |
1 |
| false |
120 |
1 |
|
T4 |
4 |
|
T33 |
3 |
|
T84 |
3 |
| true |
5546 |
1 |
|
T1 |
40 |
|
T4 |
52 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
193 |
1 |
|
T4 |
5 |
|
T33 |
9 |
|
T9 |
1 |
| others[1] |
202 |
1 |
|
T4 |
6 |
|
T5 |
1 |
|
T22 |
1 |
| others[2] |
193 |
1 |
|
T4 |
14 |
|
T33 |
7 |
|
T9 |
2 |
| others[3] |
368 |
1 |
|
T4 |
19 |
|
T22 |
2 |
|
T33 |
15 |
| false |
124 |
1 |
|
T4 |
9 |
|
T33 |
6 |
|
T114 |
1 |
| true |
5621 |
1 |
|
T1 |
40 |
|
T4 |
48 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1189 |
1 |
|
T1 |
9 |
|
T4 |
23 |
|
T42 |
1 |
| others[1] |
1238 |
1 |
|
T1 |
12 |
|
T4 |
20 |
|
T40 |
4 |
| others[2] |
1211 |
1 |
|
T1 |
3 |
|
T4 |
21 |
|
T5 |
1 |
| others[3] |
2044 |
1 |
|
T1 |
12 |
|
T4 |
31 |
|
T8 |
1 |
| false |
593 |
1 |
|
T1 |
4 |
|
T4 |
6 |
|
T7 |
1 |
| true |
426 |
1 |
|
T20 |
1 |
|
T28 |
1 |
|
T27 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1253 |
1 |
|
T1 |
13 |
|
T4 |
20 |
|
T5 |
1 |
| others[1] |
1144 |
1 |
|
T1 |
3 |
|
T4 |
15 |
|
T8 |
1 |
| others[2] |
1233 |
1 |
|
T1 |
7 |
|
T4 |
22 |
|
T28 |
1 |
| others[3] |
2021 |
1 |
|
T1 |
15 |
|
T4 |
33 |
|
T42 |
1 |
| false |
623 |
1 |
|
T1 |
2 |
|
T4 |
11 |
|
T33 |
15 |
| true |
427 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
99 |
1 |
|
T4 |
4 |
|
T33 |
4 |
|
T84 |
3 |
| others[1] |
90 |
1 |
|
T4 |
4 |
|
T22 |
1 |
|
T33 |
3 |
| others[2] |
101 |
1 |
|
T4 |
1 |
|
T33 |
4 |
|
T114 |
1 |
| others[3] |
160 |
1 |
|
T4 |
4 |
|
T22 |
1 |
|
T33 |
10 |
| false |
62 |
1 |
|
T5 |
1 |
|
T372 |
1 |
|
T84 |
2 |
| true |
6189 |
1 |
|
T1 |
40 |
|
T4 |
88 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
219 |
1 |
|
T4 |
12 |
|
T5 |
1 |
|
T20 |
1 |
| others[1] |
239 |
1 |
|
T4 |
8 |
|
T33 |
9 |
|
T319 |
1 |
| others[2] |
241 |
1 |
|
T4 |
10 |
|
T33 |
8 |
|
T25 |
1 |
| others[3] |
377 |
1 |
|
T4 |
17 |
|
T7 |
1 |
|
T22 |
1 |
| false |
121 |
1 |
|
T4 |
7 |
|
T33 |
3 |
|
T36 |
1 |
| true |
5504 |
1 |
|
T1 |
40 |
|
T4 |
47 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
973 |
1 |
|
T1 |
4 |
|
T4 |
17 |
|
T27 |
1 |
| others[1] |
1038 |
1 |
|
T1 |
9 |
|
T4 |
20 |
|
T13 |
1 |
| others[2] |
1068 |
1 |
|
T1 |
9 |
|
T4 |
20 |
|
T5 |
1 |
| others[3] |
1719 |
1 |
|
T1 |
14 |
|
T4 |
32 |
|
T40 |
1 |
| false |
555 |
1 |
|
T1 |
4 |
|
T4 |
12 |
|
T40 |
2 |
| true |
1348 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T28 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T4 |
8 |
|
T33 |
10 |
|
T24 |
1 |
| others[1] |
206 |
1 |
|
T4 |
9 |
|
T5 |
1 |
|
T33 |
10 |
| others[2] |
213 |
1 |
|
T4 |
14 |
|
T33 |
13 |
|
T95 |
1 |
| others[3] |
372 |
1 |
|
T4 |
22 |
|
T33 |
14 |
|
T31 |
1 |
| false |
108 |
1 |
|
T4 |
3 |
|
T33 |
4 |
|
T376 |
1 |
| true |
5569 |
1 |
|
T1 |
40 |
|
T4 |
45 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T4 |
12 |
|
T33 |
10 |
|
T372 |
1 |
| others[1] |
219 |
1 |
|
T4 |
12 |
|
T7 |
1 |
|
T22 |
1 |
| others[2] |
213 |
1 |
|
T4 |
8 |
|
T33 |
13 |
|
T84 |
10 |
| others[3] |
360 |
1 |
|
T4 |
19 |
|
T33 |
14 |
|
T31 |
1 |
| false |
101 |
1 |
|
T4 |
5 |
|
T33 |
2 |
|
T84 |
2 |
| true |
5592 |
1 |
|
T1 |
40 |
|
T4 |
45 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1179 |
1 |
|
T1 |
3 |
|
T4 |
20 |
|
T42 |
1 |
| others[1] |
1257 |
1 |
|
T1 |
12 |
|
T4 |
20 |
|
T13 |
1 |
| others[2] |
1184 |
1 |
|
T1 |
7 |
|
T4 |
15 |
|
T40 |
3 |
| others[3] |
2016 |
1 |
|
T1 |
14 |
|
T4 |
33 |
|
T5 |
1 |
| false |
616 |
1 |
|
T1 |
4 |
|
T4 |
13 |
|
T40 |
2 |
| true |
449 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T28 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1220 |
1 |
|
T1 |
6 |
|
T4 |
25 |
|
T33 |
18 |
| others[1] |
1228 |
1 |
|
T1 |
4 |
|
T4 |
16 |
|
T40 |
5 |
| others[2] |
1200 |
1 |
|
T1 |
7 |
|
T4 |
18 |
|
T40 |
2 |
| others[3] |
2015 |
1 |
|
T1 |
19 |
|
T4 |
31 |
|
T5 |
1 |
| false |
612 |
1 |
|
T1 |
4 |
|
T4 |
11 |
|
T33 |
11 |
| true |
426 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
105 |
1 |
|
T4 |
7 |
|
T33 |
2 |
|
T84 |
1 |
| others[1] |
103 |
1 |
|
T4 |
6 |
|
T33 |
3 |
|
T373 |
1 |
| others[2] |
89 |
1 |
|
T4 |
4 |
|
T5 |
1 |
|
T22 |
2 |
| others[3] |
192 |
1 |
|
T4 |
8 |
|
T27 |
1 |
|
T33 |
8 |
| false |
61 |
1 |
|
T4 |
4 |
|
T33 |
6 |
|
T84 |
2 |
| true |
6151 |
1 |
|
T1 |
40 |
|
T4 |
72 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
235 |
1 |
|
T4 |
9 |
|
T33 |
12 |
|
T182 |
1 |
| others[1] |
212 |
1 |
|
T4 |
9 |
|
T33 |
10 |
|
T31 |
1 |
| others[2] |
240 |
1 |
|
T4 |
7 |
|
T22 |
1 |
|
T33 |
6 |
| others[3] |
360 |
1 |
|
T4 |
14 |
|
T5 |
1 |
|
T20 |
1 |
| false |
121 |
1 |
|
T4 |
3 |
|
T33 |
4 |
|
T35 |
1 |
| true |
5533 |
1 |
|
T1 |
40 |
|
T4 |
59 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1041 |
1 |
|
T1 |
8 |
|
T4 |
18 |
|
T7 |
1 |
| others[1] |
1026 |
1 |
|
T1 |
4 |
|
T4 |
20 |
|
T8 |
1 |
| others[2] |
1012 |
1 |
|
T1 |
8 |
|
T4 |
18 |
|
T40 |
1 |
| others[3] |
1747 |
1 |
|
T1 |
15 |
|
T4 |
30 |
|
T5 |
1 |
| false |
509 |
1 |
|
T1 |
5 |
|
T4 |
15 |
|
T40 |
1 |
| true |
1366 |
1 |
|
T20 |
1 |
|
T28 |
1 |
|
T22 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
207 |
1 |
|
T4 |
9 |
|
T33 |
11 |
|
T153 |
1 |
| others[1] |
227 |
1 |
|
T4 |
7 |
|
T33 |
9 |
|
T84 |
9 |
| others[2] |
221 |
1 |
|
T4 |
14 |
|
T20 |
1 |
|
T22 |
2 |
| others[3] |
388 |
1 |
|
T4 |
22 |
|
T27 |
1 |
|
T33 |
17 |
| false |
121 |
1 |
|
T4 |
6 |
|
T22 |
1 |
|
T33 |
6 |
| true |
5537 |
1 |
|
T1 |
40 |
|
T4 |
43 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
208 |
1 |
|
T4 |
9 |
|
T33 |
10 |
|
T153 |
1 |
| others[1] |
225 |
1 |
|
T4 |
12 |
|
T33 |
8 |
|
T95 |
1 |
| others[2] |
231 |
1 |
|
T4 |
14 |
|
T33 |
13 |
|
T9 |
1 |
| others[3] |
346 |
1 |
|
T4 |
23 |
|
T7 |
1 |
|
T22 |
3 |
| false |
118 |
1 |
|
T4 |
5 |
|
T33 |
11 |
|
T84 |
6 |
| true |
5573 |
1 |
|
T1 |
40 |
|
T4 |
38 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1237 |
1 |
|
T1 |
5 |
|
T4 |
21 |
|
T8 |
1 |
| others[1] |
1208 |
1 |
|
T1 |
9 |
|
T4 |
21 |
|
T28 |
1 |
| others[2] |
1216 |
1 |
|
T1 |
6 |
|
T4 |
21 |
|
T40 |
1 |
| others[3] |
1936 |
1 |
|
T1 |
13 |
|
T4 |
26 |
|
T5 |
1 |
| false |
667 |
1 |
|
T1 |
7 |
|
T4 |
12 |
|
T40 |
3 |
| true |
437 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1205 |
1 |
|
T1 |
7 |
|
T4 |
25 |
|
T28 |
1 |
| others[1] |
1230 |
1 |
|
T1 |
8 |
|
T4 |
20 |
|
T40 |
2 |
| others[2] |
1191 |
1 |
|
T1 |
6 |
|
T4 |
15 |
|
T5 |
1 |
| others[3] |
2019 |
1 |
|
T1 |
12 |
|
T4 |
32 |
|
T8 |
1 |
| false |
632 |
1 |
|
T1 |
7 |
|
T4 |
9 |
|
T40 |
2 |
| true |
424 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
91 |
1 |
|
T4 |
4 |
|
T33 |
1 |
|
T377 |
1 |
| others[1] |
109 |
1 |
|
T4 |
4 |
|
T33 |
7 |
|
T374 |
1 |
| others[2] |
97 |
1 |
|
T4 |
4 |
|
T33 |
7 |
|
T373 |
1 |
| others[3] |
164 |
1 |
|
T4 |
8 |
|
T33 |
6 |
|
T372 |
1 |
| false |
60 |
1 |
|
T4 |
5 |
|
T33 |
4 |
|
T84 |
1 |
| true |
6180 |
1 |
|
T1 |
40 |
|
T4 |
76 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T4 |
13 |
|
T22 |
1 |
|
T33 |
12 |
| others[1] |
200 |
1 |
|
T4 |
10 |
|
T22 |
1 |
|
T33 |
8 |
| others[2] |
235 |
1 |
|
T4 |
5 |
|
T7 |
1 |
|
T33 |
9 |
| others[3] |
390 |
1 |
|
T4 |
24 |
|
T20 |
1 |
|
T33 |
22 |
| false |
146 |
1 |
|
T4 |
4 |
|
T33 |
3 |
|
T374 |
1 |
| true |
5502 |
1 |
|
T1 |
40 |
|
T4 |
45 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1022 |
1 |
|
T1 |
7 |
|
T4 |
16 |
|
T8 |
1 |
| others[1] |
981 |
1 |
|
T1 |
9 |
|
T4 |
20 |
|
T40 |
2 |
| others[2] |
1013 |
1 |
|
T1 |
8 |
|
T4 |
24 |
|
T5 |
1 |
| others[3] |
1750 |
1 |
|
T1 |
11 |
|
T4 |
32 |
|
T7 |
1 |
| false |
566 |
1 |
|
T1 |
5 |
|
T4 |
9 |
|
T40 |
1 |
| true |
1369 |
1 |
|
T20 |
1 |
|
T28 |
1 |
|
T27 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
222 |
1 |
|
T4 |
14 |
|
T33 |
12 |
|
T31 |
1 |
| others[1] |
229 |
1 |
|
T4 |
10 |
|
T22 |
1 |
|
T33 |
13 |
| others[2] |
211 |
1 |
|
T4 |
12 |
|
T28 |
1 |
|
T33 |
9 |
| others[3] |
365 |
1 |
|
T4 |
13 |
|
T20 |
1 |
|
T27 |
1 |
| false |
107 |
1 |
|
T4 |
8 |
|
T22 |
1 |
|
T33 |
4 |
| true |
5567 |
1 |
|
T1 |
40 |
|
T4 |
44 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T4 |
11 |
|
T7 |
1 |
|
T33 |
14 |
| others[1] |
204 |
1 |
|
T4 |
8 |
|
T20 |
1 |
|
T33 |
7 |
| others[2] |
214 |
1 |
|
T4 |
8 |
|
T5 |
1 |
|
T22 |
2 |
| others[3] |
371 |
1 |
|
T4 |
18 |
|
T33 |
11 |
|
T153 |
1 |
| false |
108 |
1 |
|
T4 |
3 |
|
T33 |
8 |
|
T84 |
4 |
| true |
5586 |
1 |
|
T1 |
40 |
|
T4 |
53 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1197 |
1 |
|
T1 |
8 |
|
T4 |
24 |
|
T8 |
1 |
| others[1] |
1268 |
1 |
|
T1 |
5 |
|
T4 |
17 |
|
T40 |
2 |
| others[2] |
1181 |
1 |
|
T1 |
4 |
|
T4 |
18 |
|
T5 |
1 |
| others[3] |
1974 |
1 |
|
T1 |
16 |
|
T4 |
34 |
|
T40 |
2 |
| false |
644 |
1 |
|
T1 |
7 |
|
T4 |
8 |
|
T13 |
1 |
| true |
437 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T28 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |