Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1220 |
1 |
|
T1 |
7 |
|
T4 |
19 |
|
T40 |
2 |
| others[1] |
1225 |
1 |
|
T1 |
9 |
|
T4 |
20 |
|
T42 |
1 |
| others[2] |
1186 |
1 |
|
T1 |
8 |
|
T4 |
20 |
|
T40 |
4 |
| others[3] |
2037 |
1 |
|
T1 |
15 |
|
T4 |
31 |
|
T8 |
1 |
| false |
613 |
1 |
|
T1 |
1 |
|
T4 |
11 |
|
T5 |
1 |
| true |
420 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
100 |
1 |
|
T4 |
2 |
|
T33 |
5 |
|
T84 |
1 |
| others[1] |
108 |
1 |
|
T4 |
3 |
|
T33 |
5 |
|
T373 |
1 |
| others[2] |
89 |
1 |
|
T4 |
6 |
|
T33 |
1 |
|
T84 |
1 |
| others[3] |
189 |
1 |
|
T4 |
8 |
|
T5 |
1 |
|
T33 |
10 |
| false |
56 |
1 |
|
T4 |
2 |
|
T33 |
3 |
|
T84 |
2 |
| true |
6159 |
1 |
|
T1 |
40 |
|
T4 |
80 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
246 |
1 |
|
T4 |
8 |
|
T7 |
1 |
|
T22 |
1 |
| others[1] |
201 |
1 |
|
T4 |
9 |
|
T33 |
5 |
|
T84 |
8 |
| others[2] |
230 |
1 |
|
T4 |
11 |
|
T33 |
8 |
|
T31 |
1 |
| others[3] |
369 |
1 |
|
T4 |
20 |
|
T28 |
1 |
|
T27 |
1 |
| false |
124 |
1 |
|
T4 |
5 |
|
T22 |
1 |
|
T33 |
6 |
| true |
5531 |
1 |
|
T1 |
40 |
|
T4 |
48 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1004 |
1 |
|
T1 |
3 |
|
T4 |
20 |
|
T5 |
1 |
| others[1] |
1026 |
1 |
|
T1 |
9 |
|
T4 |
20 |
|
T42 |
1 |
| others[2] |
1052 |
1 |
|
T1 |
10 |
|
T4 |
22 |
|
T40 |
1 |
| others[3] |
1690 |
1 |
|
T1 |
16 |
|
T4 |
29 |
|
T7 |
1 |
| false |
513 |
1 |
|
T1 |
2 |
|
T4 |
10 |
|
T40 |
1 |
| true |
1416 |
1 |
|
T20 |
1 |
|
T27 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T4 |
9 |
|
T5 |
1 |
|
T33 |
6 |
| others[1] |
218 |
1 |
|
T4 |
9 |
|
T7 |
1 |
|
T22 |
1 |
| others[2] |
212 |
1 |
|
T4 |
9 |
|
T33 |
8 |
|
T208 |
1 |
| others[3] |
414 |
1 |
|
T4 |
20 |
|
T28 |
1 |
|
T22 |
2 |
| false |
101 |
1 |
|
T4 |
5 |
|
T22 |
1 |
|
T33 |
4 |
| true |
5530 |
1 |
|
T1 |
40 |
|
T4 |
49 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
179 |
1 |
|
T4 |
7 |
|
T22 |
1 |
|
T33 |
9 |
| others[1] |
198 |
1 |
|
T4 |
7 |
|
T33 |
9 |
|
T31 |
1 |
| others[2] |
203 |
1 |
|
T4 |
9 |
|
T33 |
9 |
|
T377 |
1 |
| others[3] |
369 |
1 |
|
T4 |
20 |
|
T20 |
1 |
|
T27 |
1 |
| false |
114 |
1 |
|
T4 |
4 |
|
T33 |
8 |
|
T84 |
8 |
| true |
5638 |
1 |
|
T1 |
40 |
|
T4 |
54 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1139 |
1 |
|
T1 |
5 |
|
T4 |
24 |
|
T40 |
1 |
| others[1] |
1227 |
1 |
|
T1 |
7 |
|
T4 |
20 |
|
T40 |
1 |
| others[2] |
1223 |
1 |
|
T1 |
5 |
|
T4 |
15 |
|
T40 |
2 |
| others[3] |
2032 |
1 |
|
T1 |
14 |
|
T4 |
35 |
|
T5 |
1 |
| false |
617 |
1 |
|
T1 |
9 |
|
T4 |
7 |
|
T40 |
1 |
| true |
463 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1255 |
1 |
|
T1 |
7 |
|
T4 |
20 |
|
T5 |
1 |
| others[1] |
1178 |
1 |
|
T1 |
7 |
|
T4 |
13 |
|
T8 |
1 |
| others[2] |
1237 |
1 |
|
T1 |
8 |
|
T4 |
17 |
|
T28 |
1 |
| others[3] |
1954 |
1 |
|
T1 |
12 |
|
T4 |
40 |
|
T40 |
1 |
| false |
653 |
1 |
|
T1 |
6 |
|
T4 |
11 |
|
T40 |
1 |
| true |
424 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
102 |
1 |
|
T4 |
5 |
|
T33 |
4 |
|
T95 |
1 |
| others[1] |
106 |
1 |
|
T33 |
4 |
|
T84 |
4 |
|
T85 |
4 |
| others[2] |
102 |
1 |
|
T4 |
5 |
|
T33 |
3 |
|
T31 |
1 |
| others[3] |
167 |
1 |
|
T4 |
10 |
|
T5 |
1 |
|
T22 |
1 |
| false |
65 |
1 |
|
T4 |
3 |
|
T33 |
3 |
|
T85 |
4 |
| true |
6159 |
1 |
|
T1 |
40 |
|
T4 |
78 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
252 |
1 |
|
T4 |
13 |
|
T33 |
14 |
|
T35 |
1 |
| others[1] |
240 |
1 |
|
T4 |
6 |
|
T20 |
1 |
|
T22 |
1 |
| others[2] |
227 |
1 |
|
T4 |
12 |
|
T22 |
1 |
|
T33 |
10 |
| others[3] |
359 |
1 |
|
T4 |
18 |
|
T5 |
1 |
|
T33 |
21 |
| false |
101 |
1 |
|
T4 |
3 |
|
T7 |
1 |
|
T22 |
1 |
| true |
5522 |
1 |
|
T1 |
40 |
|
T4 |
49 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1023 |
1 |
|
T1 |
12 |
|
T4 |
24 |
|
T28 |
1 |
| others[1] |
1001 |
1 |
|
T1 |
10 |
|
T4 |
21 |
|
T5 |
1 |
| others[2] |
1041 |
1 |
|
T1 |
4 |
|
T4 |
18 |
|
T40 |
1 |
| others[3] |
1719 |
1 |
|
T1 |
11 |
|
T4 |
26 |
|
T8 |
1 |
| false |
501 |
1 |
|
T1 |
3 |
|
T4 |
12 |
|
T40 |
3 |
| true |
1416 |
1 |
|
T7 |
1 |
|
T13 |
1 |
|
T27 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T4 |
14 |
|
T5 |
1 |
|
T33 |
15 |
| others[1] |
208 |
1 |
|
T4 |
6 |
|
T33 |
4 |
|
T95 |
1 |
| others[2] |
193 |
1 |
|
T4 |
8 |
|
T7 |
1 |
|
T33 |
6 |
| others[3] |
391 |
1 |
|
T4 |
17 |
|
T20 |
1 |
|
T28 |
1 |
| false |
115 |
1 |
|
T4 |
2 |
|
T33 |
4 |
|
T30 |
1 |
| true |
5561 |
1 |
|
T1 |
40 |
|
T4 |
54 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
204 |
1 |
|
T4 |
13 |
|
T5 |
1 |
|
T33 |
8 |
| others[1] |
204 |
1 |
|
T4 |
5 |
|
T33 |
10 |
|
T153 |
1 |
| others[2] |
203 |
1 |
|
T4 |
9 |
|
T7 |
1 |
|
T22 |
3 |
| others[3] |
361 |
1 |
|
T4 |
14 |
|
T27 |
1 |
|
T33 |
12 |
| false |
122 |
1 |
|
T4 |
3 |
|
T33 |
11 |
|
T114 |
1 |
| true |
5607 |
1 |
|
T1 |
40 |
|
T4 |
57 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1291 |
1 |
|
T1 |
8 |
|
T4 |
16 |
|
T40 |
1 |
| others[1] |
1182 |
1 |
|
T1 |
4 |
|
T4 |
21 |
|
T8 |
1 |
| others[2] |
1130 |
1 |
|
T1 |
6 |
|
T4 |
15 |
|
T5 |
1 |
| others[3] |
2040 |
1 |
|
T1 |
12 |
|
T4 |
43 |
|
T7 |
1 |
| false |
623 |
1 |
|
T1 |
10 |
|
T4 |
6 |
|
T42 |
1 |
| true |
435 |
1 |
|
T20 |
1 |
|
T13 |
1 |
|
T28 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1196 |
1 |
|
T1 |
10 |
|
T4 |
18 |
|
T40 |
4 |
| others[1] |
1172 |
1 |
|
T1 |
8 |
|
T4 |
26 |
|
T5 |
1 |
| others[2] |
1223 |
1 |
|
T1 |
8 |
|
T4 |
21 |
|
T8 |
1 |
| others[3] |
2062 |
1 |
|
T1 |
12 |
|
T4 |
31 |
|
T40 |
3 |
| false |
616 |
1 |
|
T1 |
2 |
|
T4 |
5 |
|
T33 |
10 |
| true |
432 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
113 |
1 |
|
T4 |
4 |
|
T20 |
1 |
|
T22 |
1 |
| others[1] |
87 |
1 |
|
T4 |
4 |
|
T33 |
4 |
|
T84 |
3 |
| others[2] |
111 |
1 |
|
T4 |
4 |
|
T22 |
1 |
|
T33 |
5 |
| others[3] |
166 |
1 |
|
T4 |
8 |
|
T33 |
5 |
|
T374 |
1 |
| false |
46 |
1 |
|
T4 |
2 |
|
T33 |
2 |
|
T373 |
1 |
| true |
6178 |
1 |
|
T1 |
40 |
|
T4 |
79 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
243 |
1 |
|
T4 |
12 |
|
T5 |
1 |
|
T22 |
2 |
| others[1] |
233 |
1 |
|
T4 |
6 |
|
T33 |
9 |
|
T95 |
1 |
| others[2] |
222 |
1 |
|
T4 |
6 |
|
T33 |
7 |
|
T153 |
1 |
| others[3] |
399 |
1 |
|
T4 |
23 |
|
T20 |
1 |
|
T33 |
14 |
| false |
104 |
1 |
|
T4 |
2 |
|
T33 |
8 |
|
T319 |
1 |
| true |
5500 |
1 |
|
T1 |
40 |
|
T4 |
52 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1040 |
1 |
|
T1 |
11 |
|
T4 |
19 |
|
T42 |
1 |
| others[1] |
1026 |
1 |
|
T1 |
9 |
|
T4 |
20 |
|
T7 |
1 |
| others[2] |
1032 |
1 |
|
T1 |
12 |
|
T4 |
16 |
|
T27 |
1 |
| others[3] |
1648 |
1 |
|
T1 |
3 |
|
T4 |
40 |
|
T40 |
5 |
| false |
572 |
1 |
|
T1 |
5 |
|
T4 |
6 |
|
T5 |
1 |
| true |
1383 |
1 |
|
T20 |
1 |
|
T13 |
1 |
|
T28 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
230 |
1 |
|
T4 |
11 |
|
T7 |
1 |
|
T27 |
1 |
| others[1] |
195 |
1 |
|
T4 |
10 |
|
T5 |
1 |
|
T33 |
4 |
| others[2] |
220 |
1 |
|
T4 |
13 |
|
T20 |
1 |
|
T22 |
1 |
| others[3] |
381 |
1 |
|
T4 |
16 |
|
T22 |
1 |
|
T33 |
17 |
| false |
124 |
1 |
|
T4 |
2 |
|
T33 |
4 |
|
T182 |
1 |
| true |
5551 |
1 |
|
T1 |
40 |
|
T4 |
49 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
202 |
1 |
|
T4 |
12 |
|
T22 |
1 |
|
T33 |
7 |
| others[1] |
231 |
1 |
|
T4 |
12 |
|
T27 |
1 |
|
T22 |
1 |
| others[2] |
215 |
1 |
|
T4 |
5 |
|
T5 |
1 |
|
T22 |
1 |
| others[3] |
337 |
1 |
|
T4 |
16 |
|
T33 |
11 |
|
T153 |
1 |
| false |
104 |
1 |
|
T4 |
5 |
|
T20 |
1 |
|
T33 |
6 |
| true |
5612 |
1 |
|
T1 |
40 |
|
T4 |
51 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1211 |
1 |
|
T1 |
7 |
|
T4 |
19 |
|
T40 |
2 |
| others[1] |
1196 |
1 |
|
T1 |
5 |
|
T4 |
17 |
|
T5 |
1 |
| others[2] |
1159 |
1 |
|
T1 |
6 |
|
T4 |
18 |
|
T42 |
1 |
| others[3] |
2021 |
1 |
|
T1 |
19 |
|
T4 |
40 |
|
T40 |
5 |
| false |
674 |
1 |
|
T1 |
3 |
|
T4 |
7 |
|
T40 |
1 |
| true |
440 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1258 |
1 |
|
T1 |
4 |
|
T4 |
28 |
|
T40 |
3 |
| others[1] |
1201 |
1 |
|
T1 |
7 |
|
T4 |
14 |
|
T5 |
1 |
| others[2] |
1154 |
1 |
|
T1 |
11 |
|
T4 |
21 |
|
T42 |
1 |
| others[3] |
2033 |
1 |
|
T1 |
16 |
|
T4 |
25 |
|
T40 |
5 |
| false |
630 |
1 |
|
T1 |
2 |
|
T4 |
13 |
|
T33 |
10 |
| true |
425 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
114 |
1 |
|
T4 |
2 |
|
T22 |
1 |
|
T33 |
3 |
| others[1] |
94 |
1 |
|
T4 |
4 |
|
T33 |
3 |
|
T84 |
3 |
| others[2] |
112 |
1 |
|
T4 |
8 |
|
T33 |
5 |
|
T305 |
1 |
| others[3] |
169 |
1 |
|
T4 |
4 |
|
T5 |
1 |
|
T33 |
7 |
| false |
51 |
1 |
|
T4 |
1 |
|
T33 |
3 |
|
T84 |
3 |
| true |
6161 |
1 |
|
T1 |
40 |
|
T4 |
82 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
214 |
1 |
|
T4 |
8 |
|
T28 |
1 |
|
T27 |
1 |
| others[1] |
228 |
1 |
|
T4 |
7 |
|
T7 |
1 |
|
T22 |
1 |
| others[2] |
240 |
1 |
|
T4 |
10 |
|
T33 |
16 |
|
T31 |
1 |
| others[3] |
366 |
1 |
|
T4 |
21 |
|
T5 |
1 |
|
T20 |
1 |
| false |
127 |
1 |
|
T4 |
7 |
|
T33 |
9 |
|
T372 |
1 |
| true |
5526 |
1 |
|
T1 |
40 |
|
T4 |
48 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
990 |
1 |
|
T1 |
7 |
|
T4 |
16 |
|
T28 |
1 |
| others[1] |
1047 |
1 |
|
T1 |
9 |
|
T4 |
17 |
|
T42 |
1 |
| others[2] |
1039 |
1 |
|
T1 |
8 |
|
T4 |
20 |
|
T22 |
2 |
| others[3] |
1696 |
1 |
|
T1 |
13 |
|
T4 |
35 |
|
T5 |
1 |
| false |
561 |
1 |
|
T1 |
3 |
|
T4 |
13 |
|
T40 |
2 |
| true |
1368 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
213 |
1 |
|
T4 |
9 |
|
T33 |
10 |
|
T30 |
1 |
| others[1] |
226 |
1 |
|
T4 |
11 |
|
T27 |
1 |
|
T33 |
7 |
| others[2] |
206 |
1 |
|
T4 |
7 |
|
T33 |
16 |
|
T24 |
1 |
| others[3] |
347 |
1 |
|
T4 |
16 |
|
T22 |
1 |
|
T33 |
10 |
| false |
103 |
1 |
|
T4 |
4 |
|
T33 |
6 |
|
T182 |
1 |
| true |
5606 |
1 |
|
T1 |
40 |
|
T4 |
54 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
210 |
1 |
|
T4 |
10 |
|
T33 |
7 |
|
T376 |
1 |
| others[1] |
223 |
1 |
|
T4 |
9 |
|
T33 |
14 |
|
T31 |
1 |
| others[2] |
218 |
1 |
|
T4 |
12 |
|
T33 |
8 |
|
T95 |
1 |
| others[3] |
368 |
1 |
|
T4 |
19 |
|
T5 |
1 |
|
T33 |
20 |
| false |
111 |
1 |
|
T4 |
7 |
|
T22 |
2 |
|
T33 |
2 |
| true |
5571 |
1 |
|
T1 |
40 |
|
T4 |
44 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1194 |
1 |
|
T1 |
7 |
|
T4 |
18 |
|
T40 |
2 |
| others[1] |
1203 |
1 |
|
T1 |
6 |
|
T4 |
24 |
|
T5 |
1 |
| others[2] |
1199 |
1 |
|
T1 |
7 |
|
T4 |
18 |
|
T40 |
3 |
| others[3] |
1974 |
1 |
|
T1 |
12 |
|
T4 |
26 |
|
T40 |
2 |
| false |
690 |
1 |
|
T1 |
8 |
|
T4 |
15 |
|
T40 |
1 |
| true |
441 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
6 |
1 |
|
T81 |
1 |
|
T125 |
1 |
|
T133 |
1 |
| others[1] |
14 |
1 |
|
T13 |
1 |
|
T16 |
1 |
|
T378 |
1 |
| others[2] |
9 |
1 |
|
T12 |
1 |
|
T147 |
1 |
|
T379 |
1 |
| others[3] |
11 |
1 |
|
T62 |
1 |
|
T148 |
1 |
|
T304 |
1 |
| false |
4 |
1 |
|
T380 |
1 |
|
T381 |
1 |
|
T382 |
1 |
| true |
53 |
1 |
|
T12 |
1 |
|
T57 |
1 |
|
T138 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1 |
1 |
|
T34 |
1 |
|
- |
- |
|
- |
- |
| others[1] |
3 |
1 |
|
T159 |
1 |
|
T383 |
1 |
|
T384 |
1 |
| others[2] |
2 |
1 |
|
T158 |
1 |
|
T385 |
1 |
|
- |
- |
| others[3] |
3 |
1 |
|
T386 |
1 |
|
T387 |
1 |
|
T388 |
1 |
| false |
10 |
1 |
|
T389 |
1 |
|
T390 |
1 |
|
T391 |
1 |
| true |
25 |
1 |
|
T157 |
1 |
|
T160 |
1 |
|
T392 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2 |
1 |
|
T158 |
1 |
|
T393 |
1 |
|
- |
- |
| others[1] |
3 |
1 |
|
T160 |
1 |
|
T394 |
1 |
|
T395 |
1 |
| others[2] |
2 |
1 |
|
T396 |
1 |
|
T397 |
1 |
|
- |
- |
| others[3] |
6 |
1 |
|
T391 |
1 |
|
T398 |
1 |
|
T399 |
1 |
| false |
7 |
1 |
|
T34 |
1 |
|
T400 |
1 |
|
T383 |
1 |
| true |
24 |
1 |
|
T157 |
1 |
|
T159 |
1 |
|
T392 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |