Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10409 |
1 |
|
T1 |
8 |
|
T4 |
23 |
|
T6 |
1 |
| others[1] |
724 |
1 |
|
T1 |
6 |
|
T4 |
21 |
|
T5 |
1 |
| others[2] |
703 |
1 |
|
T1 |
6 |
|
T4 |
16 |
|
T8 |
1 |
| others[3] |
1300 |
1 |
|
T1 |
15 |
|
T4 |
30 |
|
T40 |
3 |
| false |
404 |
1 |
|
T1 |
5 |
|
T4 |
11 |
|
T33 |
12 |
| true |
520 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2350 |
1 |
|
T1 |
10 |
|
T4 |
12 |
|
T33 |
8 |
| others[1] |
2373 |
1 |
|
T1 |
6 |
|
T4 |
7 |
|
T6 |
1 |
| others[2] |
2379 |
1 |
|
T1 |
7 |
|
T4 |
9 |
|
T8 |
1 |
| others[3] |
4109 |
1 |
|
T1 |
11 |
|
T4 |
16 |
|
T42 |
1 |
| false |
1266 |
1 |
|
T1 |
6 |
|
T4 |
5 |
|
T5 |
1 |
| true |
1583 |
1 |
|
T4 |
52 |
|
T7 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9829 |
1 |
|
T4 |
6 |
|
T22 |
1 |
|
T33 |
10 |
| others[1] |
263 |
1 |
|
T4 |
6 |
|
T28 |
1 |
|
T33 |
12 |
| others[2] |
266 |
1 |
|
T4 |
15 |
|
T22 |
1 |
|
T33 |
14 |
| others[3] |
458 |
1 |
|
T4 |
17 |
|
T7 |
1 |
|
T42 |
1 |
| false |
136 |
1 |
|
T4 |
6 |
|
T27 |
1 |
|
T22 |
2 |
| true |
3108 |
1 |
|
T1 |
40 |
|
T4 |
51 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10036 |
1 |
|
T1 |
4 |
|
T4 |
8 |
|
T6 |
1 |
| others[1] |
460 |
1 |
|
T1 |
1 |
|
T4 |
9 |
|
T13 |
1 |
| others[2] |
483 |
1 |
|
T1 |
7 |
|
T4 |
6 |
|
T40 |
4 |
| others[3] |
735 |
1 |
|
T1 |
3 |
|
T4 |
19 |
|
T20 |
1 |
| false |
219 |
1 |
|
T1 |
2 |
|
T4 |
1 |
|
T33 |
6 |
| true |
2127 |
1 |
|
T1 |
23 |
|
T4 |
58 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9835 |
1 |
|
T4 |
13 |
|
T28 |
1 |
|
T22 |
2 |
| others[1] |
249 |
1 |
|
T4 |
6 |
|
T22 |
1 |
|
T33 |
6 |
| others[2] |
249 |
1 |
|
T4 |
13 |
|
T20 |
1 |
|
T27 |
1 |
| others[3] |
426 |
1 |
|
T4 |
15 |
|
T7 |
1 |
|
T8 |
1 |
| false |
118 |
1 |
|
T4 |
6 |
|
T33 |
6 |
|
T182 |
2 |
| true |
3183 |
1 |
|
T1 |
40 |
|
T4 |
48 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9797 |
1 |
|
T4 |
5 |
|
T5 |
1 |
|
T20 |
1 |
| others[1] |
259 |
1 |
|
T4 |
11 |
|
T33 |
10 |
|
T95 |
1 |
| others[2] |
229 |
1 |
|
T4 |
12 |
|
T7 |
1 |
|
T33 |
12 |
| others[3] |
400 |
1 |
|
T4 |
15 |
|
T22 |
1 |
|
T33 |
12 |
| false |
136 |
1 |
|
T4 |
5 |
|
T27 |
1 |
|
T22 |
1 |
| true |
3239 |
1 |
|
T1 |
40 |
|
T4 |
53 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10332 |
1 |
|
T1 |
8 |
|
T4 |
20 |
|
T6 |
1 |
| others[1] |
740 |
1 |
|
T1 |
8 |
|
T4 |
15 |
|
T13 |
1 |
| others[2] |
741 |
1 |
|
T1 |
4 |
|
T4 |
23 |
|
T40 |
5 |
| others[3] |
1312 |
1 |
|
T1 |
15 |
|
T4 |
36 |
|
T5 |
1 |
| false |
406 |
1 |
|
T1 |
5 |
|
T4 |
7 |
|
T40 |
2 |
| true |
529 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T28 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10345 |
1 |
|
T1 |
8 |
|
T4 |
19 |
|
T6 |
1 |
| others[1] |
726 |
1 |
|
T1 |
7 |
|
T4 |
23 |
|
T33 |
19 |
| others[2] |
758 |
1 |
|
T1 |
8 |
|
T4 |
19 |
|
T40 |
3 |
| others[3] |
1234 |
1 |
|
T1 |
11 |
|
T4 |
32 |
|
T42 |
1 |
| false |
423 |
1 |
|
T1 |
6 |
|
T4 |
8 |
|
T5 |
1 |
| true |
540 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2412 |
1 |
|
T1 |
10 |
|
T4 |
13 |
|
T6 |
1 |
| others[1] |
2340 |
1 |
|
T1 |
7 |
|
T4 |
8 |
|
T40 |
2 |
| others[2] |
2383 |
1 |
|
T1 |
7 |
|
T4 |
11 |
|
T20 |
1 |
| others[3] |
4089 |
1 |
|
T1 |
13 |
|
T4 |
13 |
|
T5 |
1 |
| false |
1282 |
1 |
|
T1 |
3 |
|
T4 |
4 |
|
T8 |
1 |
| true |
1520 |
1 |
|
T4 |
52 |
|
T7 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9809 |
1 |
|
T4 |
9 |
|
T20 |
1 |
|
T42 |
1 |
| others[1] |
248 |
1 |
|
T4 |
7 |
|
T33 |
11 |
|
T32 |
1 |
| others[2] |
271 |
1 |
|
T4 |
7 |
|
T33 |
8 |
|
T95 |
1 |
| others[3] |
479 |
1 |
|
T4 |
17 |
|
T7 |
1 |
|
T8 |
1 |
| false |
148 |
1 |
|
T4 |
9 |
|
T5 |
1 |
|
T33 |
8 |
| true |
3071 |
1 |
|
T1 |
40 |
|
T4 |
52 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10025 |
1 |
|
T1 |
5 |
|
T4 |
13 |
|
T5 |
1 |
| others[1] |
474 |
1 |
|
T1 |
6 |
|
T4 |
9 |
|
T40 |
1 |
| others[2] |
460 |
1 |
|
T1 |
5 |
|
T4 |
8 |
|
T40 |
1 |
| others[3] |
759 |
1 |
|
T1 |
4 |
|
T4 |
12 |
|
T8 |
1 |
| false |
273 |
1 |
|
T4 |
4 |
|
T40 |
1 |
|
T33 |
3 |
| true |
2035 |
1 |
|
T1 |
20 |
|
T4 |
55 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9818 |
1 |
|
T4 |
7 |
|
T33 |
6 |
|
T31 |
1 |
| others[1] |
257 |
1 |
|
T4 |
10 |
|
T27 |
1 |
|
T33 |
5 |
| others[2] |
250 |
1 |
|
T4 |
11 |
|
T7 |
1 |
|
T33 |
7 |
| others[3] |
436 |
1 |
|
T4 |
16 |
|
T5 |
1 |
|
T22 |
2 |
| false |
132 |
1 |
|
T4 |
5 |
|
T22 |
1 |
|
T33 |
8 |
| true |
3133 |
1 |
|
T1 |
40 |
|
T4 |
52 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9794 |
1 |
|
T4 |
6 |
|
T5 |
1 |
|
T20 |
1 |
| others[1] |
258 |
1 |
|
T4 |
10 |
|
T22 |
2 |
|
T33 |
8 |
| others[2] |
265 |
1 |
|
T4 |
12 |
|
T22 |
1 |
|
T33 |
10 |
| others[3] |
432 |
1 |
|
T4 |
17 |
|
T27 |
1 |
|
T22 |
1 |
| false |
108 |
1 |
|
T4 |
1 |
|
T33 |
3 |
|
T51 |
1 |
| true |
3169 |
1 |
|
T1 |
40 |
|
T4 |
55 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10313 |
1 |
|
T1 |
5 |
|
T4 |
16 |
|
T6 |
1 |
| others[1] |
731 |
1 |
|
T1 |
8 |
|
T4 |
19 |
|
T8 |
1 |
| others[2] |
791 |
1 |
|
T1 |
10 |
|
T4 |
25 |
|
T13 |
1 |
| others[3] |
1293 |
1 |
|
T1 |
12 |
|
T4 |
33 |
|
T5 |
1 |
| false |
385 |
1 |
|
T1 |
5 |
|
T4 |
8 |
|
T40 |
1 |
| true |
513 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T28 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10331 |
1 |
|
T1 |
5 |
|
T4 |
18 |
|
T6 |
1 |
| others[1] |
765 |
1 |
|
T1 |
7 |
|
T4 |
21 |
|
T40 |
1 |
| others[2] |
754 |
1 |
|
T1 |
13 |
|
T4 |
22 |
|
T42 |
1 |
| others[3] |
1276 |
1 |
|
T1 |
11 |
|
T4 |
34 |
|
T5 |
1 |
| false |
368 |
1 |
|
T1 |
4 |
|
T4 |
6 |
|
T40 |
2 |
| true |
532 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2437 |
1 |
|
T1 |
3 |
|
T4 |
6 |
|
T8 |
1 |
| others[1] |
2434 |
1 |
|
T1 |
13 |
|
T4 |
12 |
|
T40 |
2 |
| others[2] |
2356 |
1 |
|
T1 |
5 |
|
T4 |
10 |
|
T42 |
1 |
| others[3] |
4002 |
1 |
|
T1 |
13 |
|
T4 |
16 |
|
T5 |
1 |
| false |
1281 |
1 |
|
T1 |
6 |
|
T4 |
4 |
|
T6 |
1 |
| true |
1516 |
1 |
|
T4 |
53 |
|
T7 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9848 |
1 |
|
T4 |
6 |
|
T22 |
1 |
|
T33 |
11 |
| others[1] |
286 |
1 |
|
T4 |
13 |
|
T22 |
1 |
|
T33 |
11 |
| others[2] |
265 |
1 |
|
T4 |
9 |
|
T20 |
1 |
|
T22 |
1 |
| others[3] |
428 |
1 |
|
T4 |
18 |
|
T5 |
1 |
|
T42 |
1 |
| false |
135 |
1 |
|
T4 |
8 |
|
T33 |
7 |
|
T182 |
1 |
| true |
3064 |
1 |
|
T1 |
40 |
|
T4 |
47 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10005 |
1 |
|
T1 |
3 |
|
T4 |
9 |
|
T6 |
1 |
| others[1] |
445 |
1 |
|
T1 |
5 |
|
T4 |
8 |
|
T40 |
2 |
| others[2] |
440 |
1 |
|
T1 |
3 |
|
T4 |
8 |
|
T42 |
1 |
| others[3] |
804 |
1 |
|
T1 |
7 |
|
T4 |
18 |
|
T5 |
1 |
| false |
224 |
1 |
|
T1 |
6 |
|
T4 |
7 |
|
T40 |
1 |
| true |
2108 |
1 |
|
T1 |
16 |
|
T4 |
51 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9811 |
1 |
|
T4 |
10 |
|
T5 |
1 |
|
T7 |
1 |
| others[1] |
257 |
1 |
|
T4 |
11 |
|
T8 |
1 |
|
T22 |
1 |
| others[2] |
241 |
1 |
|
T4 |
7 |
|
T33 |
9 |
|
T376 |
1 |
| others[3] |
427 |
1 |
|
T4 |
18 |
|
T28 |
1 |
|
T22 |
1 |
| false |
129 |
1 |
|
T4 |
3 |
|
T20 |
1 |
|
T42 |
1 |
| true |
3161 |
1 |
|
T1 |
40 |
|
T4 |
52 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9789 |
1 |
|
T4 |
9 |
|
T22 |
1 |
|
T33 |
8 |
| others[1] |
242 |
1 |
|
T4 |
9 |
|
T22 |
1 |
|
T33 |
9 |
| others[2] |
256 |
1 |
|
T4 |
14 |
|
T5 |
1 |
|
T7 |
1 |
| others[3] |
405 |
1 |
|
T4 |
17 |
|
T27 |
1 |
|
T22 |
1 |
| false |
136 |
1 |
|
T4 |
3 |
|
T42 |
1 |
|
T33 |
3 |
| true |
3198 |
1 |
|
T1 |
40 |
|
T4 |
49 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10285 |
1 |
|
T1 |
7 |
|
T4 |
18 |
|
T6 |
1 |
| others[1] |
796 |
1 |
|
T1 |
7 |
|
T4 |
23 |
|
T5 |
1 |
| others[2] |
764 |
1 |
|
T1 |
11 |
|
T4 |
14 |
|
T8 |
1 |
| others[3] |
1255 |
1 |
|
T1 |
12 |
|
T4 |
34 |
|
T7 |
1 |
| false |
414 |
1 |
|
T1 |
3 |
|
T4 |
12 |
|
T40 |
1 |
| true |
512 |
1 |
|
T20 |
1 |
|
T13 |
1 |
|
T27 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10303 |
1 |
|
T1 |
4 |
|
T4 |
19 |
|
T6 |
1 |
| others[1] |
774 |
1 |
|
T1 |
12 |
|
T4 |
21 |
|
T40 |
4 |
| others[2] |
785 |
1 |
|
T1 |
7 |
|
T4 |
24 |
|
T5 |
1 |
| others[3] |
1263 |
1 |
|
T1 |
10 |
|
T4 |
29 |
|
T8 |
1 |
| false |
378 |
1 |
|
T1 |
7 |
|
T4 |
8 |
|
T33 |
12 |
| true |
523 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2392 |
1 |
|
T1 |
8 |
|
T4 |
8 |
|
T22 |
1 |
| others[1] |
2423 |
1 |
|
T1 |
8 |
|
T4 |
9 |
|
T40 |
4 |
| others[2] |
2378 |
1 |
|
T1 |
7 |
|
T4 |
9 |
|
T20 |
1 |
| others[3] |
4012 |
1 |
|
T1 |
16 |
|
T4 |
9 |
|
T5 |
1 |
| false |
1270 |
1 |
|
T1 |
1 |
|
T4 |
5 |
|
T6 |
1 |
| true |
1551 |
1 |
|
T4 |
61 |
|
T7 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9835 |
1 |
|
T4 |
8 |
|
T8 |
1 |
|
T27 |
1 |
| others[1] |
252 |
1 |
|
T4 |
7 |
|
T20 |
1 |
|
T33 |
11 |
| others[2] |
274 |
1 |
|
T4 |
8 |
|
T7 |
1 |
|
T33 |
18 |
| others[3] |
447 |
1 |
|
T4 |
22 |
|
T22 |
1 |
|
T33 |
12 |
| false |
131 |
1 |
|
T4 |
8 |
|
T42 |
1 |
|
T33 |
5 |
| true |
3087 |
1 |
|
T1 |
40 |
|
T4 |
48 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10015 |
1 |
|
T1 |
6 |
|
T4 |
11 |
|
T6 |
1 |
| others[1] |
463 |
1 |
|
T1 |
1 |
|
T4 |
14 |
|
T40 |
1 |
| others[2] |
466 |
1 |
|
T1 |
5 |
|
T4 |
13 |
|
T22 |
1 |
| others[3] |
746 |
1 |
|
T1 |
6 |
|
T4 |
16 |
|
T27 |
1 |
| false |
251 |
1 |
|
T1 |
6 |
|
T4 |
6 |
|
T33 |
5 |
| true |
2085 |
1 |
|
T1 |
16 |
|
T4 |
41 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9799 |
1 |
|
T4 |
12 |
|
T22 |
1 |
|
T33 |
14 |
| others[1] |
261 |
1 |
|
T4 |
11 |
|
T7 |
1 |
|
T8 |
1 |
| others[2] |
236 |
1 |
|
T4 |
10 |
|
T33 |
6 |
|
T31 |
1 |
| others[3] |
449 |
1 |
|
T4 |
13 |
|
T5 |
1 |
|
T22 |
1 |
| false |
141 |
1 |
|
T4 |
7 |
|
T33 |
3 |
|
T92 |
1 |
| true |
3140 |
1 |
|
T1 |
40 |
|
T4 |
48 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9797 |
1 |
|
T4 |
15 |
|
T8 |
1 |
|
T42 |
1 |
| others[1] |
270 |
1 |
|
T4 |
11 |
|
T5 |
1 |
|
T22 |
3 |
| others[2] |
261 |
1 |
|
T4 |
6 |
|
T33 |
12 |
|
T96 |
1 |
| others[3] |
393 |
1 |
|
T4 |
12 |
|
T22 |
1 |
|
T33 |
16 |
| false |
127 |
1 |
|
T4 |
4 |
|
T33 |
1 |
|
T55 |
1 |
| true |
3178 |
1 |
|
T1 |
40 |
|
T4 |
53 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10322 |
1 |
|
T1 |
7 |
|
T4 |
24 |
|
T6 |
1 |
| others[1] |
735 |
1 |
|
T1 |
8 |
|
T4 |
19 |
|
T13 |
1 |
| others[2] |
767 |
1 |
|
T1 |
6 |
|
T4 |
17 |
|
T5 |
1 |
| others[3] |
1267 |
1 |
|
T1 |
16 |
|
T4 |
32 |
|
T40 |
7 |
| false |
405 |
1 |
|
T1 |
3 |
|
T4 |
9 |
|
T40 |
1 |
| true |
530 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T28 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10365 |
1 |
|
T1 |
6 |
|
T4 |
24 |
|
T6 |
1 |
| others[1] |
771 |
1 |
|
T1 |
7 |
|
T4 |
17 |
|
T5 |
1 |
| others[2] |
762 |
1 |
|
T1 |
10 |
|
T4 |
22 |
|
T8 |
1 |
| others[3] |
1185 |
1 |
|
T1 |
10 |
|
T4 |
30 |
|
T40 |
5 |
| false |
405 |
1 |
|
T1 |
7 |
|
T4 |
8 |
|
T33 |
13 |
| true |
538 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2408 |
1 |
|
T1 |
6 |
|
T4 |
13 |
|
T40 |
2 |
| others[1] |
2498 |
1 |
|
T1 |
11 |
|
T4 |
16 |
|
T6 |
1 |
| others[2] |
2279 |
1 |
|
T1 |
5 |
|
T4 |
8 |
|
T40 |
3 |
| others[3] |
3975 |
1 |
|
T1 |
12 |
|
T4 |
14 |
|
T42 |
1 |
| false |
1285 |
1 |
|
T1 |
6 |
|
T4 |
2 |
|
T33 |
6 |
| true |
1581 |
1 |
|
T4 |
48 |
|
T5 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9815 |
1 |
|
T4 |
4 |
|
T7 |
1 |
|
T22 |
2 |
| others[1] |
282 |
1 |
|
T4 |
11 |
|
T5 |
1 |
|
T28 |
1 |
| others[2] |
265 |
1 |
|
T4 |
9 |
|
T27 |
1 |
|
T33 |
6 |
| others[3] |
455 |
1 |
|
T4 |
18 |
|
T33 |
10 |
|
T24 |
1 |
| false |
136 |
1 |
|
T4 |
9 |
|
T22 |
2 |
|
T33 |
6 |
| true |
3073 |
1 |
|
T1 |
40 |
|
T4 |
50 |
|
T6 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |