Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10030 |
1 |
|
T1 |
4 |
|
T4 |
9 |
|
T6 |
1 |
| others[1] |
418 |
1 |
|
T1 |
3 |
|
T4 |
10 |
|
T40 |
2 |
| others[2] |
428 |
1 |
|
T1 |
3 |
|
T4 |
11 |
|
T22 |
1 |
| others[3] |
803 |
1 |
|
T1 |
8 |
|
T4 |
23 |
|
T28 |
1 |
| false |
226 |
1 |
|
T1 |
2 |
|
T4 |
4 |
|
T5 |
1 |
| true |
2121 |
1 |
|
T1 |
20 |
|
T4 |
44 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9826 |
1 |
|
T4 |
13 |
|
T28 |
1 |
|
T33 |
13 |
| others[1] |
234 |
1 |
|
T4 |
7 |
|
T33 |
8 |
|
T24 |
1 |
| others[2] |
238 |
1 |
|
T4 |
9 |
|
T27 |
1 |
|
T33 |
10 |
| others[3] |
443 |
1 |
|
T4 |
15 |
|
T8 |
1 |
|
T33 |
11 |
| false |
131 |
1 |
|
T4 |
7 |
|
T42 |
1 |
|
T22 |
1 |
| true |
3154 |
1 |
|
T1 |
40 |
|
T4 |
50 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9785 |
1 |
|
T4 |
9 |
|
T42 |
1 |
|
T33 |
13 |
| others[1] |
255 |
1 |
|
T4 |
10 |
|
T5 |
1 |
|
T8 |
1 |
| others[2] |
256 |
1 |
|
T4 |
12 |
|
T33 |
8 |
|
T224 |
1 |
| others[3] |
404 |
1 |
|
T4 |
11 |
|
T27 |
1 |
|
T33 |
19 |
| false |
111 |
1 |
|
T4 |
4 |
|
T20 |
1 |
|
T33 |
3 |
| true |
3215 |
1 |
|
T1 |
40 |
|
T4 |
55 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10327 |
1 |
|
T1 |
11 |
|
T4 |
17 |
|
T5 |
1 |
| others[1] |
771 |
1 |
|
T1 |
10 |
|
T4 |
14 |
|
T40 |
3 |
| others[2] |
796 |
1 |
|
T1 |
5 |
|
T4 |
11 |
|
T40 |
1 |
| others[3] |
1211 |
1 |
|
T1 |
12 |
|
T4 |
47 |
|
T8 |
1 |
| false |
423 |
1 |
|
T1 |
2 |
|
T4 |
12 |
|
T33 |
14 |
| true |
498 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10333 |
1 |
|
T1 |
7 |
|
T4 |
23 |
|
T6 |
1 |
| others[1] |
759 |
1 |
|
T1 |
3 |
|
T4 |
17 |
|
T5 |
1 |
| others[2] |
808 |
1 |
|
T1 |
9 |
|
T4 |
18 |
|
T40 |
2 |
| others[3] |
1236 |
1 |
|
T1 |
19 |
|
T4 |
36 |
|
T40 |
6 |
| false |
373 |
1 |
|
T1 |
2 |
|
T4 |
7 |
|
T33 |
9 |
| true |
517 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2378 |
1 |
|
T1 |
7 |
|
T4 |
9 |
|
T42 |
1 |
| others[1] |
2432 |
1 |
|
T1 |
5 |
|
T4 |
14 |
|
T40 |
3 |
| others[2] |
2416 |
1 |
|
T1 |
10 |
|
T4 |
12 |
|
T6 |
1 |
| others[3] |
4030 |
1 |
|
T1 |
15 |
|
T4 |
11 |
|
T8 |
1 |
| false |
1257 |
1 |
|
T1 |
3 |
|
T4 |
3 |
|
T40 |
1 |
| true |
1513 |
1 |
|
T4 |
52 |
|
T5 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9847 |
1 |
|
T4 |
10 |
|
T7 |
1 |
|
T22 |
1 |
| others[1] |
281 |
1 |
|
T4 |
7 |
|
T22 |
1 |
|
T33 |
7 |
| others[2] |
274 |
1 |
|
T4 |
10 |
|
T5 |
1 |
|
T42 |
1 |
| others[3] |
441 |
1 |
|
T4 |
15 |
|
T27 |
1 |
|
T33 |
17 |
| false |
152 |
1 |
|
T4 |
6 |
|
T33 |
3 |
|
T95 |
1 |
| true |
3031 |
1 |
|
T1 |
40 |
|
T4 |
53 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10020 |
1 |
|
T1 |
8 |
|
T4 |
11 |
|
T6 |
1 |
| others[1] |
448 |
1 |
|
T1 |
3 |
|
T4 |
15 |
|
T13 |
1 |
| others[2] |
467 |
1 |
|
T1 |
4 |
|
T4 |
11 |
|
T5 |
1 |
| others[3] |
758 |
1 |
|
T1 |
6 |
|
T4 |
13 |
|
T8 |
1 |
| false |
223 |
1 |
|
T1 |
2 |
|
T4 |
3 |
|
T33 |
4 |
| true |
2110 |
1 |
|
T1 |
17 |
|
T4 |
48 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9822 |
1 |
|
T4 |
13 |
|
T5 |
1 |
|
T22 |
1 |
| others[1] |
270 |
1 |
|
T4 |
9 |
|
T20 |
1 |
|
T22 |
1 |
| others[2] |
246 |
1 |
|
T4 |
11 |
|
T8 |
1 |
|
T22 |
1 |
| others[3] |
397 |
1 |
|
T4 |
13 |
|
T33 |
14 |
|
T96 |
1 |
| false |
138 |
1 |
|
T4 |
11 |
|
T28 |
1 |
|
T33 |
5 |
| true |
3153 |
1 |
|
T1 |
40 |
|
T4 |
44 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9798 |
1 |
|
T4 |
8 |
|
T33 |
6 |
|
T62 |
2 |
| others[1] |
250 |
1 |
|
T4 |
15 |
|
T22 |
1 |
|
T33 |
14 |
| others[2] |
233 |
1 |
|
T4 |
6 |
|
T5 |
1 |
|
T20 |
1 |
| others[3] |
413 |
1 |
|
T4 |
16 |
|
T22 |
1 |
|
T33 |
11 |
| false |
113 |
1 |
|
T4 |
4 |
|
T7 |
1 |
|
T33 |
7 |
| true |
3219 |
1 |
|
T1 |
40 |
|
T4 |
52 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10343 |
1 |
|
T1 |
8 |
|
T4 |
17 |
|
T6 |
1 |
| others[1] |
737 |
1 |
|
T1 |
4 |
|
T4 |
18 |
|
T42 |
1 |
| others[2] |
760 |
1 |
|
T1 |
5 |
|
T4 |
26 |
|
T40 |
3 |
| others[3] |
1267 |
1 |
|
T1 |
19 |
|
T4 |
31 |
|
T8 |
1 |
| false |
429 |
1 |
|
T1 |
4 |
|
T4 |
9 |
|
T5 |
1 |
| true |
490 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10329 |
1 |
|
T1 |
5 |
|
T4 |
23 |
|
T6 |
1 |
| others[1] |
720 |
1 |
|
T1 |
6 |
|
T4 |
18 |
|
T42 |
1 |
| others[2] |
761 |
1 |
|
T1 |
14 |
|
T4 |
13 |
|
T5 |
1 |
| others[3] |
1272 |
1 |
|
T1 |
11 |
|
T4 |
37 |
|
T40 |
2 |
| false |
402 |
1 |
|
T1 |
4 |
|
T4 |
10 |
|
T33 |
11 |
| true |
542 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2432 |
1 |
|
T1 |
8 |
|
T4 |
11 |
|
T40 |
5 |
| others[1] |
2423 |
1 |
|
T1 |
12 |
|
T4 |
9 |
|
T20 |
1 |
| others[2] |
2423 |
1 |
|
T1 |
4 |
|
T4 |
7 |
|
T6 |
1 |
| others[3] |
3937 |
1 |
|
T1 |
14 |
|
T4 |
15 |
|
T8 |
1 |
| false |
1292 |
1 |
|
T1 |
2 |
|
T4 |
6 |
|
T33 |
4 |
| true |
1519 |
1 |
|
T4 |
53 |
|
T5 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9832 |
1 |
|
T4 |
20 |
|
T22 |
1 |
|
T33 |
7 |
| others[1] |
273 |
1 |
|
T4 |
10 |
|
T5 |
1 |
|
T8 |
1 |
| others[2] |
233 |
1 |
|
T4 |
8 |
|
T20 |
1 |
|
T33 |
5 |
| others[3] |
422 |
1 |
|
T4 |
10 |
|
T7 |
1 |
|
T33 |
20 |
| false |
153 |
1 |
|
T4 |
8 |
|
T33 |
5 |
|
T24 |
1 |
| true |
3113 |
1 |
|
T1 |
40 |
|
T4 |
45 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10015 |
1 |
|
T1 |
1 |
|
T4 |
10 |
|
T6 |
1 |
| others[1] |
415 |
1 |
|
T1 |
5 |
|
T4 |
11 |
|
T20 |
1 |
| others[2] |
446 |
1 |
|
T1 |
4 |
|
T4 |
7 |
|
T22 |
4 |
| others[3] |
719 |
1 |
|
T1 |
4 |
|
T4 |
20 |
|
T40 |
4 |
| false |
267 |
1 |
|
T1 |
3 |
|
T4 |
4 |
|
T28 |
1 |
| true |
2164 |
1 |
|
T1 |
23 |
|
T4 |
49 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9844 |
1 |
|
T4 |
11 |
|
T8 |
1 |
|
T42 |
1 |
| others[1] |
242 |
1 |
|
T4 |
5 |
|
T5 |
1 |
|
T27 |
1 |
| others[2] |
238 |
1 |
|
T4 |
11 |
|
T33 |
9 |
|
T224 |
1 |
| others[3] |
456 |
1 |
|
T4 |
20 |
|
T22 |
1 |
|
T33 |
22 |
| false |
132 |
1 |
|
T4 |
7 |
|
T33 |
7 |
|
T332 |
1 |
| true |
3114 |
1 |
|
T1 |
40 |
|
T4 |
47 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9798 |
1 |
|
T4 |
11 |
|
T27 |
1 |
|
T22 |
1 |
| others[1] |
233 |
1 |
|
T4 |
9 |
|
T33 |
8 |
|
T96 |
1 |
| others[2] |
257 |
1 |
|
T4 |
10 |
|
T33 |
7 |
|
T372 |
1 |
| others[3] |
402 |
1 |
|
T4 |
13 |
|
T7 |
1 |
|
T22 |
1 |
| false |
137 |
1 |
|
T4 |
5 |
|
T42 |
1 |
|
T33 |
6 |
| true |
3199 |
1 |
|
T1 |
40 |
|
T4 |
53 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10334 |
1 |
|
T1 |
8 |
|
T4 |
16 |
|
T6 |
1 |
| others[1] |
762 |
1 |
|
T1 |
8 |
|
T4 |
19 |
|
T8 |
1 |
| others[2] |
784 |
1 |
|
T1 |
6 |
|
T4 |
23 |
|
T5 |
1 |
| others[3] |
1254 |
1 |
|
T1 |
13 |
|
T4 |
34 |
|
T42 |
1 |
| false |
399 |
1 |
|
T1 |
5 |
|
T4 |
9 |
|
T33 |
11 |
| true |
493 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10312 |
1 |
|
T1 |
10 |
|
T4 |
17 |
|
T6 |
1 |
| others[1] |
766 |
1 |
|
T1 |
10 |
|
T4 |
23 |
|
T8 |
1 |
| others[2] |
753 |
1 |
|
T1 |
4 |
|
T4 |
18 |
|
T40 |
5 |
| others[3] |
1281 |
1 |
|
T1 |
13 |
|
T4 |
26 |
|
T5 |
1 |
| false |
384 |
1 |
|
T1 |
3 |
|
T4 |
17 |
|
T33 |
10 |
| true |
530 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2372 |
1 |
|
T1 |
8 |
|
T4 |
12 |
|
T40 |
2 |
| others[1] |
2435 |
1 |
|
T1 |
10 |
|
T4 |
7 |
|
T5 |
1 |
| others[2] |
2351 |
1 |
|
T1 |
9 |
|
T4 |
11 |
|
T42 |
1 |
| others[3] |
4082 |
1 |
|
T1 |
11 |
|
T4 |
12 |
|
T20 |
1 |
| false |
1263 |
1 |
|
T1 |
2 |
|
T4 |
2 |
|
T6 |
1 |
| true |
1523 |
1 |
|
T4 |
57 |
|
T7 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9811 |
1 |
|
T4 |
7 |
|
T22 |
2 |
|
T33 |
7 |
| others[1] |
268 |
1 |
|
T4 |
8 |
|
T5 |
1 |
|
T42 |
1 |
| others[2] |
250 |
1 |
|
T4 |
7 |
|
T33 |
12 |
|
T55 |
1 |
| others[3] |
442 |
1 |
|
T4 |
14 |
|
T8 |
1 |
|
T33 |
18 |
| false |
138 |
1 |
|
T4 |
5 |
|
T33 |
4 |
|
T24 |
1 |
| true |
3117 |
1 |
|
T1 |
40 |
|
T4 |
60 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10016 |
1 |
|
T1 |
3 |
|
T4 |
12 |
|
T5 |
1 |
| others[1] |
467 |
1 |
|
T1 |
4 |
|
T4 |
11 |
|
T40 |
1 |
| others[2] |
445 |
1 |
|
T1 |
4 |
|
T4 |
4 |
|
T8 |
1 |
| others[3] |
762 |
1 |
|
T1 |
5 |
|
T4 |
16 |
|
T28 |
1 |
| false |
230 |
1 |
|
T1 |
3 |
|
T4 |
7 |
|
T40 |
1 |
| true |
2106 |
1 |
|
T1 |
21 |
|
T4 |
51 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9795 |
1 |
|
T4 |
3 |
|
T33 |
10 |
|
T24 |
1 |
| others[1] |
245 |
1 |
|
T4 |
14 |
|
T20 |
1 |
|
T33 |
8 |
| others[2] |
257 |
1 |
|
T4 |
8 |
|
T22 |
2 |
|
T33 |
10 |
| others[3] |
434 |
1 |
|
T4 |
22 |
|
T5 |
1 |
|
T7 |
1 |
| false |
139 |
1 |
|
T4 |
5 |
|
T28 |
1 |
|
T33 |
5 |
| true |
3156 |
1 |
|
T1 |
40 |
|
T4 |
49 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9810 |
1 |
|
T4 |
11 |
|
T8 |
1 |
|
T27 |
1 |
| others[1] |
250 |
1 |
|
T4 |
15 |
|
T5 |
1 |
|
T22 |
2 |
| others[2] |
236 |
1 |
|
T4 |
5 |
|
T33 |
10 |
|
T31 |
1 |
| others[3] |
404 |
1 |
|
T4 |
16 |
|
T33 |
16 |
|
T95 |
1 |
| false |
129 |
1 |
|
T4 |
5 |
|
T22 |
2 |
|
T33 |
6 |
| true |
3197 |
1 |
|
T1 |
40 |
|
T4 |
49 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10311 |
1 |
|
T1 |
3 |
|
T4 |
17 |
|
T6 |
1 |
| others[1] |
737 |
1 |
|
T1 |
6 |
|
T4 |
18 |
|
T28 |
1 |
| others[2] |
809 |
1 |
|
T1 |
6 |
|
T4 |
24 |
|
T40 |
3 |
| others[3] |
1274 |
1 |
|
T1 |
17 |
|
T4 |
31 |
|
T5 |
1 |
| false |
384 |
1 |
|
T1 |
8 |
|
T4 |
11 |
|
T40 |
2 |
| true |
511 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T13 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |