Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	226527	1		T1	36		T4	100		T5	168
auto[FlashEraseBank]	252304	1		T1	4		T4	1166		T5	32

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	261750	1		T1	40		T4	577		T5	76
auto[FlashOpProgram]	197337	1		T4	644		T5	91		T6	1
auto[FlashOpErase]	15744	1		T4	45		T5	33		T6	1
auto[FlashOpInvalid]	4000	1		T97	200		T193	200		T194	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	261750	1		T1	40		T4	577		T5	76
op[FlashOpProgram]	197337	1		T4	644		T5	91		T6	1
op[FlashOpErase]	15744	1		T4	45		T5	33		T6	1
read_erase_read	696	1		T4	3		T5	6		T33	4
read_prog_read	1160	1		T5	12		T42	5		T22	2

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	339740	1		T1	40		T4	96		T5	194
auto[FlashPartInfo]	135372	1		T4	1170		T5	6		T7	240
auto[FlashPartInfo1]	866	1		T7	3		T42	4		T92	3
auto[FlashPartInfo2]	2853	1		T7	8		T42	15		T53	2

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	199407	1		T1	40		T4	32		T5	75
auto[FlashPartData]	auto[FlashOpProgram]	132818	1		T4	35		T5	88		T6	1
auto[FlashPartData]	auto[FlashOpErase]	3617	1		T4	29		T5	31		T6	1
auto[FlashPartData]	auto[FlashOpInvalid]	3898	1		T97	192		T193	198		T194	196
auto[FlashPartInfo]	auto[FlashOpRead]	59903	1		T4	545		T5	1		T7	240
auto[FlashPartInfo]	auto[FlashOpProgram]	63277	1		T4	609		T5	3		T42	302
auto[FlashPartInfo]	auto[FlashOpErase]	12106	1		T4	16		T5	2		T33	17
auto[FlashPartInfo]	auto[FlashOpInvalid]	86	1		T97	6		T193	2		T194	4
auto[FlashPartInfo1]	auto[FlashOpRead]	694	1		T7	3		T42	4		T92	3
auto[FlashPartInfo1]	auto[FlashOpProgram]	162	1		T87	32		T102	32		T103	1
auto[FlashPartInfo1]	auto[FlashOpErase]	6	1		T86	2		T103	1		T403	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	4	1		T103	2		T404	2		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1746	1		T7	8		T42	4		T53	2
auto[FlashPartInfo2]	auto[FlashOpProgram]	1080	1		T42	11		T83	6		T51	8
auto[FlashPartInfo2]	auto[FlashOpErase]	15	1		T97	1		T89	1		T101	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	12	1		T97	2		T405	4		T406	2