Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.48	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	4	28	87.50

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	4	28	87.50	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30686	1		T4	20		T5	12		T6	4
auto[1]	9	1		T161	3		T273	2		T336	1
auto[2]	118	1		T86	4		T116	8		T191	5
auto[3]	190	1		T25	1		T30	3		T337	1

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7763	1		T4	5		T5	3		T6	1
evic_idx[1]	7761	1		T4	5		T5	3		T6	1
evic_idx[2]	7739	1		T4	5		T5	3		T6	1
evic_idx[3]	7740	1		T4	5		T5	3		T6	1

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	29905	1		T6	4		T112	1		T171	700
evic_op[2]	497	1		T40	1		T33	4		T25	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	4	28	87.50	4

Automatically Generated Cross Bins for evic_all_cross

Element holes

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
*	[evic_op[1]]	[auto[1]]	--	--	4

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7440	1		T6	1		T171	175		T97	100
evic_idx[0]	evic_op[1]	auto[2]	2	1		T338	2		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	47	1		T339	4		T340	7		T341	9
evic_idx[0]	evic_op[2]	auto[0]	86	1		T33	1		T342	1		T84	1
evic_idx[0]	evic_op[2]	auto[1]	2	1		T161	1		T343	1		-	-
evic_idx[0]	evic_op[2]	auto[2]	19	1		T344	4		T345	11		T346	4
evic_idx[0]	evic_op[2]	auto[3]	16	1		T30	1		T337	1		T98	1
evic_idx[1]	evic_op[1]	auto[0]	7443	1		T6	1		T112	1		T171	175
evic_idx[1]	evic_op[1]	auto[2]	2	1		T338	2		-	-		-	-
evic_idx[1]	evic_op[1]	auto[3]	32	1		T339	3		T340	4		T341	7
evic_idx[1]	evic_op[2]	auto[0]	89	1		T33	1		T204	1		T342	1
evic_idx[1]	evic_op[2]	auto[1]	2	1		T161	1		T343	1		-	-
evic_idx[1]	evic_op[2]	auto[2]	27	1		T191	3		T344	8		T347	1
evic_idx[1]	evic_op[2]	auto[3]	15	1		T25	1		T30	1		T98	1
evic_idx[2]	evic_op[1]	auto[0]	7441	1		T6	1		T171	175		T97	100
evic_idx[2]	evic_op[1]	auto[2]	2	1		T338	2		-	-		-	-
evic_idx[2]	evic_op[1]	auto[3]	27	1		T339	4		T340	3		T341	5
evic_idx[2]	evic_op[2]	auto[0]	86	1		T40	1		T33	1		T342	1
evic_idx[2]	evic_op[2]	auto[1]	1	1		T273	1		-	-		-	-
evic_idx[2]	evic_op[2]	auto[2]	19	1		T191	2		T344	5		T347	1
evic_idx[2]	evic_op[2]	auto[3]	13	1		T30	1		T183	1		T348	1
evic_idx[3]	evic_op[1]	auto[0]	7443	1		T6	1		T171	175		T97	100
evic_idx[3]	evic_op[1]	auto[2]	2	1		T338	2		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	24	1		T339	3		T340	4		T341	7
evic_idx[3]	evic_op[2]	auto[0]	81	1		T33	1		T342	1		T84	1
evic_idx[3]	evic_op[2]	auto[1]	4	1		T161	1		T273	1		T336	1
evic_idx[3]	evic_op[2]	auto[2]	21	1		T269	1		T349	1		T344	6
evic_idx[3]	evic_op[2]	auto[3]	16	1		T183	1		T37	1		T314	1