Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	15138	1		T28	2162		T328	2665		T329	10311
rd_lvl[2]	43326	1		T28	1628		T272	1773		T330	5506
rd_lvl[3]	23356	1		T28	780		T272	1533		T330	407
rd_lvl[4]	30832	1		T28	889		T272	322		T331	3682
rd_lvl[5]	15955	1		T28	598		T332	1757		T319	1587
rd_lvl[6]	14789	1		T28	145		T332	934		T319	588
rd_lvl[7]	12806	1		T28	489		T47	650		T208	1241
rd_lvl[8]	14897	1		T8	1187		T28	543		T47	1034
rd_lvl[9]	6815	1		T8	129		T28	684		T24	209
rd_lvl[10]	5578	1		T28	250		T24	656		T47	96
rd_lvl[11]	5255	1		T28	231		T319	53		T36	626
rd_lvl[12]	3505	1		T28	2		T24	23		T272	62
rd_lvl[13]	5936	1		T55	667		T35	275		T36	2
rd_lvl[14]	5425	1		T28	87		T55	304		T35	599
rd_lvl[15]	4777	1		T333	506		T334	655		T335	452