Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	309958	1		T1	2		T2	1		T3	1
all_pins[1]	309958	1		T1	2		T2	1		T3	1
all_pins[2]	309958	1		T1	2		T2	1		T3	1
all_pins[3]	309958	1		T1	2		T2	1		T3	1
all_pins[4]	309958	1		T1	2		T2	1		T3	1
all_pins[5]	309958	1		T1	2		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1540134	1		T1	12		T2	6		T3	6
values[0x1]	319614	1		T8	1974		T28	9465		T27	1304
transitions[0x0=>0x1]	289978	1		T8	1316		T28	8510		T27	1304
transitions[0x1=>0x0]	289965	1		T8	1316		T28	8510		T27	1304

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	309807	1		T1	2		T2	1		T3	1
all_pins[0]	values[0x1]	151	1		T246	1		T247	1		T248	5
all_pins[0]	transitions[0x0=>0x1]	94	1		T247	1		T248	5		T321	5
all_pins[0]	transitions[0x1=>0x0]	82	1		T246	5		T247	7		T320	1
all_pins[1]	values[0x0]	309819	1		T1	2		T2	1		T3	1
all_pins[1]	values[0x1]	139	1		T246	6		T247	7		T320	1
all_pins[1]	transitions[0x0=>0x1]	107	1		T246	4		T247	5		T323	2
all_pins[1]	transitions[0x1=>0x0]	3152	1		T334	293		T335	40		T268	401
all_pins[2]	values[0x0]	306774	1		T1	2		T2	1		T3	1
all_pins[2]	values[0x1]	3184	1		T334	293		T335	40		T268	401
all_pins[2]	transitions[0x0=>0x1]	46	1		T246	2		T247	2		T248	1
all_pins[2]	transitions[0x1=>0x0]	209454	1		T8	1316		T28	8488		T24	888
all_pins[3]	values[0x0]	97366	1		T1	2		T2	1		T3	1
all_pins[3]	values[0x1]	212592	1		T8	1316		T28	8488		T24	888
all_pins[3]	transitions[0x0=>0x1]	186243	1		T8	658		T28	7533		T24	888
all_pins[3]	transitions[0x1=>0x0]	77133	1		T28	22		T27	1304		T24	888
all_pins[4]	values[0x0]	206476	1		T1	2		T2	1		T3	1
all_pins[4]	values[0x1]	103482	1		T8	658		T28	977		T27	1304
all_pins[4]	transitions[0x0=>0x1]	103461	1		T8	658		T28	977		T27	1304
all_pins[4]	transitions[0x1=>0x0]	45	1		T246	1		T247	4		T321	1
all_pins[5]	values[0x0]	309892	1		T1	2		T2	1		T3	1
all_pins[5]	values[0x1]	66	1		T246	2		T247	4		T248	2
all_pins[5]	transitions[0x0=>0x1]	27	1		T247	4		T320	2		T353	2
all_pins[5]	transitions[0x1=>0x0]	99	1		T247	1		T248	2		T321	4