Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	272	1		T246	7		T247	7		T248	4
all_values[1]	272	1		T246	7		T247	7		T248	4
all_values[2]	272	1		T246	7		T247	7		T248	4
all_values[3]	272	1		T246	7		T247	7		T248	4
all_values[4]	272	1		T246	7		T247	7		T248	4
all_values[5]	272	1		T246	7		T247	7		T248	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	860	1		T246	22		T247	17		T248	12
auto[1]	772	1		T246	20		T247	25		T248	12

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	549	1		T246	10		T247	12		T248	5
auto[1]	1083	1		T246	32		T247	30		T248	19

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	974	1		T246	19		T247	23		T248	12
auto[1]	658	1		T246	23		T247	19		T248	12

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	79	1		T246	2		T247	4		T320	4
all_values[0]	auto[0]	auto[1]	auto[1]	75	1		T246	2		T248	1		T321	2
all_values[0]	auto[1]	auto[0]	auto[1]	67	1		T246	3		T247	3		T248	1
all_values[0]	auto[1]	auto[1]	auto[1]	51	1		T248	2		T321	2		T320	1
all_values[1]	auto[0]	auto[0]	auto[1]	94	1		T246	2		T247	1		T248	4
all_values[1]	auto[0]	auto[1]	auto[1]	70	1		T246	2		T247	3		T320	1
all_values[1]	auto[1]	auto[0]	auto[1]	56	1		T246	1		T321	1		T320	1
all_values[1]	auto[1]	auto[1]	auto[1]	52	1		T246	2		T247	3		T320	1
all_values[2]	auto[0]	auto[0]	auto[0]	86	1		T246	2		T247	1		T248	1
all_values[2]	auto[0]	auto[1]	auto[0]	73	1		T246	1		T247	4		T248	1
all_values[2]	auto[1]	auto[0]	auto[1]	60	1		T246	1		T248	2		T320	1
all_values[2]	auto[1]	auto[1]	auto[1]	53	1		T246	3		T247	2		T320	1
all_values[3]	auto[0]	auto[0]	auto[0]	81	1		T247	1		T321	1		T320	5
all_values[3]	auto[0]	auto[1]	auto[0]	87	1		T246	3		T247	3		T248	1
all_values[3]	auto[1]	auto[0]	auto[1]	57	1		T246	3		T248	2		T321	3
all_values[3]	auto[1]	auto[1]	auto[1]	47	1		T246	1		T247	3		T248	1
all_values[4]	auto[0]	auto[0]	auto[0]	54	1		T320	2		T322	1		T323	2
all_values[4]	auto[0]	auto[0]	auto[1]	30	1		T246	1		T247	1		T324	1
all_values[4]	auto[0]	auto[1]	auto[0]	55	1		T246	2		T247	3		T248	1
all_values[4]	auto[0]	auto[1]	auto[1]	24	1		T248	1		T321	1		T320	1
all_values[4]	auto[1]	auto[0]	auto[1]	61	1		T246	4		T247	3		T248	1
all_values[4]	auto[1]	auto[1]	auto[1]	48	1		T248	1		T320	1		T322	2
all_values[5]	auto[0]	auto[0]	auto[0]	58	1		T246	1		T248	1		T321	1
all_values[5]	auto[0]	auto[0]	auto[1]	19	1		T325	1		T326	1		T327	2
all_values[5]	auto[0]	auto[1]	auto[0]	55	1		T246	1		T320	1		T323	1
all_values[5]	auto[0]	auto[1]	auto[1]	34	1		T247	2		T248	1		T321	1
all_values[5]	auto[1]	auto[0]	auto[1]	58	1		T246	2		T247	3		T321	1
all_values[5]	auto[1]	auto[1]	auto[1]	48	1		T246	3		T247	2		T248	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal