| T1083 |
/workspace/coverage/default/3.flash_ctrl_host_dir_rd.673553266 |
|
|
Apr 25 01:44:05 PM PDT 24 |
Apr 25 01:44:41 PM PDT 24 |
34581200 ps |
| T1084 |
/workspace/coverage/default/0.flash_ctrl_phy_arb.3760490671 |
|
|
Apr 25 01:42:36 PM PDT 24 |
Apr 25 01:51:03 PM PDT 24 |
781920200 ps |
| T1085 |
/workspace/coverage/default/36.flash_ctrl_alert_test.656566487 |
|
|
Apr 25 01:50:58 PM PDT 24 |
Apr 25 01:51:12 PM PDT 24 |
98996100 ps |
| T1086 |
/workspace/coverage/default/13.flash_ctrl_hw_sec_otp.3627985847 |
|
|
Apr 25 01:47:19 PM PDT 24 |
Apr 25 01:49:16 PM PDT 24 |
4815482500 ps |
| T1087 |
/workspace/coverage/default/1.flash_ctrl_ro.3114303513 |
|
|
Apr 25 01:43:20 PM PDT 24 |
Apr 25 01:45:00 PM PDT 24 |
941539900 ps |
| T1088 |
/workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.1769247285 |
|
|
Apr 25 01:48:48 PM PDT 24 |
Apr 25 01:51:06 PM PDT 24 |
10012376200 ps |
| T1089 |
/workspace/coverage/default/20.flash_ctrl_alert_test.1983011248 |
|
|
Apr 25 01:49:13 PM PDT 24 |
Apr 25 01:49:27 PM PDT 24 |
178840300 ps |
| T1090 |
/workspace/coverage/default/48.flash_ctrl_otp_reset.2343900503 |
|
|
Apr 25 01:51:46 PM PDT 24 |
Apr 25 01:53:36 PM PDT 24 |
73210200 ps |
| T1091 |
/workspace/coverage/default/34.flash_ctrl_sec_info_access.446879126 |
|
|
Apr 25 01:50:48 PM PDT 24 |
Apr 25 01:51:52 PM PDT 24 |
1541646000 ps |
| T1092 |
/workspace/coverage/default/2.flash_ctrl_error_mp.3648038086 |
|
|
Apr 25 01:43:43 PM PDT 24 |
Apr 25 02:21:01 PM PDT 24 |
6002017500 ps |
| T15 |
/workspace/coverage/default/1.flash_ctrl_phy_host_grant_err.1145015144 |
|
|
Apr 25 01:43:34 PM PDT 24 |
Apr 25 01:43:49 PM PDT 24 |
43732300 ps |
| T1093 |
/workspace/coverage/default/22.flash_ctrl_hw_sec_otp.3152100448 |
|
|
Apr 25 01:49:20 PM PDT 24 |
Apr 25 01:51:24 PM PDT 24 |
3382609600 ps |
| T1094 |
/workspace/coverage/default/5.flash_ctrl_mp_regions.1879254568 |
|
|
Apr 25 01:45:05 PM PDT 24 |
Apr 25 01:55:07 PM PDT 24 |
15286907500 ps |
| T1095 |
/workspace/coverage/default/5.flash_ctrl_rw_evict_all_en.740402322 |
|
|
Apr 25 01:45:21 PM PDT 24 |
Apr 25 01:45:53 PM PDT 24 |
31976500 ps |
| T1096 |
/workspace/coverage/default/37.flash_ctrl_connect.696968239 |
|
|
Apr 25 01:51:04 PM PDT 24 |
Apr 25 01:51:21 PM PDT 24 |
38957300 ps |
| T1097 |
/workspace/coverage/default/2.flash_ctrl_re_evict.399955679 |
|
|
Apr 25 01:43:57 PM PDT 24 |
Apr 25 01:44:34 PM PDT 24 |
157853600 ps |
| T1098 |
/workspace/coverage/default/1.flash_ctrl_smoke.1606328279 |
|
|
Apr 25 01:43:07 PM PDT 24 |
Apr 25 01:45:30 PM PDT 24 |
33426000 ps |
| T1099 |
/workspace/coverage/default/27.flash_ctrl_hw_sec_otp.1389417582 |
|
|
Apr 25 01:50:02 PM PDT 24 |
Apr 25 01:50:47 PM PDT 24 |
968343900 ps |
| T1100 |
/workspace/coverage/default/41.flash_ctrl_connect.1942909134 |
|
|
Apr 25 01:51:20 PM PDT 24 |
Apr 25 01:51:37 PM PDT 24 |
14001900 ps |
| T1101 |
/workspace/coverage/default/8.flash_ctrl_invalid_op.657777269 |
|
|
Apr 25 01:46:07 PM PDT 24 |
Apr 25 01:47:39 PM PDT 24 |
1943367900 ps |
| T346 |
/workspace/coverage/default/0.flash_ctrl_rw_evict_all_en.2741492839 |
|
|
Apr 25 01:42:55 PM PDT 24 |
Apr 25 01:43:32 PM PDT 24 |
805303400 ps |
| T1102 |
/workspace/coverage/default/14.flash_ctrl_alert_test.1671136768 |
|
|
Apr 25 01:47:54 PM PDT 24 |
Apr 25 01:48:08 PM PDT 24 |
121992900 ps |
| T387 |
/workspace/coverage/default/2.flash_ctrl_sec_info_access.3848185360 |
|
|
Apr 25 01:44:00 PM PDT 24 |
Apr 25 01:45:10 PM PDT 24 |
5469345700 ps |
| T1103 |
/workspace/coverage/default/4.flash_ctrl_error_prog_type.2524004161 |
|
|
Apr 25 01:44:37 PM PDT 24 |
Apr 25 02:28:45 PM PDT 24 |
1500582300 ps |
| T1104 |
/workspace/coverage/default/19.flash_ctrl_otp_reset.3726404118 |
|
|
Apr 25 01:48:57 PM PDT 24 |
Apr 25 01:51:08 PM PDT 24 |
41595900 ps |
| T1105 |
/workspace/coverage/default/16.flash_ctrl_intr_rd_slow_flash.3310479384 |
|
|
Apr 25 01:48:16 PM PDT 24 |
Apr 25 01:51:23 PM PDT 24 |
12537729500 ps |
| T1106 |
/workspace/coverage/default/4.flash_ctrl_stress_all.145713174 |
|
|
Apr 25 01:44:54 PM PDT 24 |
Apr 25 01:45:33 PM PDT 24 |
46465200 ps |
| T1107 |
/workspace/coverage/default/11.flash_ctrl_wo.1135985343 |
|
|
Apr 25 01:46:53 PM PDT 24 |
Apr 25 01:50:01 PM PDT 24 |
4447881000 ps |
| T1108 |
/workspace/coverage/default/4.flash_ctrl_alert_test.3162411559 |
|
|
Apr 25 01:45:01 PM PDT 24 |
Apr 25 01:45:16 PM PDT 24 |
256139600 ps |
| T1109 |
/workspace/coverage/default/8.flash_ctrl_hw_rma_reset.3518956766 |
|
|
Apr 25 01:46:06 PM PDT 24 |
Apr 25 02:02:38 PM PDT 24 |
160192512800 ps |
| T1110 |
/workspace/coverage/default/21.flash_ctrl_rw_evict_all_en.1189674825 |
|
|
Apr 25 01:49:14 PM PDT 24 |
Apr 25 01:49:45 PM PDT 24 |
38098700 ps |
| T1111 |
/workspace/coverage/default/4.flash_ctrl_read_word_sweep_derr.828577210 |
|
|
Apr 25 01:44:50 PM PDT 24 |
Apr 25 01:45:13 PM PDT 24 |
62407400 ps |
| T1112 |
/workspace/coverage/default/34.flash_ctrl_rw_evict.597768883 |
|
|
Apr 25 01:50:47 PM PDT 24 |
Apr 25 01:51:21 PM PDT 24 |
56882100 ps |
| T1113 |
/workspace/coverage/default/24.flash_ctrl_intr_rd_slow_flash.4264593762 |
|
|
Apr 25 01:49:38 PM PDT 24 |
Apr 25 01:53:52 PM PDT 24 |
37558205000 ps |
| T1114 |
/workspace/coverage/default/5.flash_ctrl_rw_derr.3478511422 |
|
|
Apr 25 01:45:13 PM PDT 24 |
Apr 25 01:52:58 PM PDT 24 |
7206060800 ps |
| T1115 |
/workspace/coverage/default/21.flash_ctrl_alert_test.3076216812 |
|
|
Apr 25 01:49:23 PM PDT 24 |
Apr 25 01:49:37 PM PDT 24 |
42055100 ps |
| T1116 |
/workspace/coverage/default/0.flash_ctrl_sw_op.2198514434 |
|
|
Apr 25 01:42:35 PM PDT 24 |
Apr 25 01:43:02 PM PDT 24 |
36251900 ps |
| T1117 |
/workspace/coverage/default/18.flash_ctrl_otp_reset.111442318 |
|
|
Apr 25 01:48:44 PM PDT 24 |
Apr 25 01:50:33 PM PDT 24 |
356372200 ps |
| T1118 |
/workspace/coverage/default/38.flash_ctrl_otp_reset.1752003081 |
|
|
Apr 25 01:51:07 PM PDT 24 |
Apr 25 01:53:20 PM PDT 24 |
38943600 ps |
| T1119 |
/workspace/coverage/default/5.flash_ctrl_hw_read_seed_err.4035981929 |
|
|
Apr 25 01:45:19 PM PDT 24 |
Apr 25 01:45:33 PM PDT 24 |
48761500 ps |
| T1120 |
/workspace/coverage/default/5.flash_ctrl_otp_reset.981857152 |
|
|
Apr 25 01:45:07 PM PDT 24 |
Apr 25 01:46:56 PM PDT 24 |
127751500 ps |
| T1121 |
/workspace/coverage/default/67.flash_ctrl_connect.950995459 |
|
|
Apr 25 01:52:02 PM PDT 24 |
Apr 25 01:52:16 PM PDT 24 |
23151400 ps |
| T1122 |
/workspace/coverage/default/10.flash_ctrl_smoke.2552838471 |
|
|
Apr 25 01:46:40 PM PDT 24 |
Apr 25 01:48:16 PM PDT 24 |
53179900 ps |
| T1123 |
/workspace/coverage/default/9.flash_ctrl_prog_reset.505002237 |
|
|
Apr 25 01:46:33 PM PDT 24 |
Apr 25 01:46:47 PM PDT 24 |
59198500 ps |
| T1124 |
/workspace/coverage/default/14.flash_ctrl_hw_rma_reset.3091094962 |
|
|
Apr 25 01:47:38 PM PDT 24 |
Apr 25 02:01:21 PM PDT 24 |
160169410800 ps |
| T1125 |
/workspace/coverage/default/60.flash_ctrl_connect.2644753940 |
|
|
Apr 25 01:52:01 PM PDT 24 |
Apr 25 01:52:18 PM PDT 24 |
13300900 ps |
| T388 |
/workspace/coverage/default/3.flash_ctrl_sec_info_access.959171530 |
|
|
Apr 25 01:44:33 PM PDT 24 |
Apr 25 01:45:28 PM PDT 24 |
700411500 ps |
| T1126 |
/workspace/coverage/default/4.flash_ctrl_wo.729133315 |
|
|
Apr 25 01:44:41 PM PDT 24 |
Apr 25 01:47:37 PM PDT 24 |
4066196400 ps |
| T1127 |
/workspace/coverage/default/17.flash_ctrl_disable.631118884 |
|
|
Apr 25 01:48:39 PM PDT 24 |
Apr 25 01:49:02 PM PDT 24 |
13178100 ps |
| T1128 |
/workspace/coverage/default/1.flash_ctrl_rd_buff_evict.239975428 |
|
|
Apr 25 01:43:17 PM PDT 24 |
Apr 25 01:44:58 PM PDT 24 |
85505800 ps |
| T1129 |
/workspace/coverage/default/6.flash_ctrl_smoke.2960249936 |
|
|
Apr 25 01:45:19 PM PDT 24 |
Apr 25 01:46:12 PM PDT 24 |
48955300 ps |
| T1130 |
/workspace/coverage/default/2.flash_ctrl_alert_test.654693922 |
|
|
Apr 25 01:44:01 PM PDT 24 |
Apr 25 01:44:15 PM PDT 24 |
43946300 ps |
| T1131 |
/workspace/coverage/default/3.flash_ctrl_error_prog_type.3878958233 |
|
|
Apr 25 01:44:12 PM PDT 24 |
Apr 25 02:19:30 PM PDT 24 |
475245400 ps |
| T1132 |
/workspace/coverage/default/28.flash_ctrl_disable.720287502 |
|
|
Apr 25 01:50:07 PM PDT 24 |
Apr 25 01:50:28 PM PDT 24 |
15726500 ps |
| T1133 |
/workspace/coverage/default/2.flash_ctrl_ro_serr.2421295115 |
|
|
Apr 25 01:43:50 PM PDT 24 |
Apr 25 01:45:54 PM PDT 24 |
598156700 ps |
| T1134 |
/workspace/coverage/default/8.flash_ctrl_smoke.4105459115 |
|
|
Apr 25 01:46:01 PM PDT 24 |
Apr 25 01:49:14 PM PDT 24 |
142136700 ps |
| T1135 |
/workspace/coverage/default/19.flash_ctrl_wo.2159905770 |
|
|
Apr 25 01:48:59 PM PDT 24 |
Apr 25 01:51:52 PM PDT 24 |
8080542700 ps |
| T1136 |
/workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.1146318900 |
|
|
Apr 25 01:50:11 PM PDT 24 |
Apr 25 01:52:57 PM PDT 24 |
15108431600 ps |
| T1137 |
/workspace/coverage/default/42.flash_ctrl_connect.2894267553 |
|
|
Apr 25 01:51:27 PM PDT 24 |
Apr 25 01:51:43 PM PDT 24 |
129833100 ps |
| T1138 |
/workspace/coverage/default/10.flash_ctrl_rw.728461877 |
|
|
Apr 25 01:46:47 PM PDT 24 |
Apr 25 01:56:08 PM PDT 24 |
12177679800 ps |
| T1139 |
/workspace/coverage/default/10.flash_ctrl_intr_rd_slow_flash.2315152260 |
|
|
Apr 25 01:46:45 PM PDT 24 |
Apr 25 01:50:25 PM PDT 24 |
32766909400 ps |
| T63 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.2603876237 |
|
|
Apr 25 12:39:01 PM PDT 24 |
Apr 25 12:46:49 PM PDT 24 |
348970100 ps |
| T64 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.1729736094 |
|
|
Apr 25 12:38:41 PM PDT 24 |
Apr 25 12:39:00 PM PDT 24 |
300767100 ps |
| T65 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.1076853230 |
|
|
Apr 25 12:38:56 PM PDT 24 |
Apr 25 12:53:55 PM PDT 24 |
1302047600 ps |
| T197 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.1802186242 |
|
|
Apr 25 12:39:04 PM PDT 24 |
Apr 25 12:39:23 PM PDT 24 |
226631600 ps |
| T198 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.1543247203 |
|
|
Apr 25 12:38:45 PM PDT 24 |
Apr 25 12:39:07 PM PDT 24 |
391870900 ps |
| T231 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3104137375 |
|
|
Apr 25 12:38:51 PM PDT 24 |
Apr 25 12:39:29 PM PDT 24 |
883248800 ps |
| T246 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.453690480 |
|
|
Apr 25 12:39:13 PM PDT 24 |
Apr 25 12:39:32 PM PDT 24 |
124976300 ps |
| T232 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3264359545 |
|
|
Apr 25 12:38:54 PM PDT 24 |
Apr 25 12:39:14 PM PDT 24 |
355193700 ps |
| T247 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.1326820484 |
|
|
Apr 25 12:39:01 PM PDT 24 |
Apr 25 12:39:16 PM PDT 24 |
27112800 ps |
| T248 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.792946200 |
|
|
Apr 25 12:39:13 PM PDT 24 |
Apr 25 12:39:31 PM PDT 24 |
53692900 ps |
| T321 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.3922529820 |
|
|
Apr 25 12:39:09 PM PDT 24 |
Apr 25 12:39:25 PM PDT 24 |
15803800 ps |
| T320 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.792708624 |
|
|
Apr 25 12:39:00 PM PDT 24 |
Apr 25 12:39:15 PM PDT 24 |
25432100 ps |
| T322 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.374015009 |
|
|
Apr 25 12:39:01 PM PDT 24 |
Apr 25 12:39:16 PM PDT 24 |
27108000 ps |
| T323 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.392003842 |
|
|
Apr 25 12:39:17 PM PDT 24 |
Apr 25 12:39:40 PM PDT 24 |
28910700 ps |
| T324 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.1943701947 |
|
|
Apr 25 12:38:56 PM PDT 24 |
Apr 25 12:39:11 PM PDT 24 |
32311300 ps |
| T199 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.1757639045 |
|
|
Apr 25 12:38:56 PM PDT 24 |
Apr 25 12:39:14 PM PDT 24 |
37614100 ps |
| T200 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.1108089001 |
|
|
Apr 25 12:38:55 PM PDT 24 |
Apr 25 12:39:13 PM PDT 24 |
48985200 ps |
| T233 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3696587947 |
|
|
Apr 25 12:39:03 PM PDT 24 |
Apr 25 12:39:23 PM PDT 24 |
1423387100 ps |
| T1140 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3116452780 |
|
|
Apr 25 12:39:08 PM PDT 24 |
Apr 25 12:39:24 PM PDT 24 |
21583100 ps |
| T1141 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.1966933609 |
|
|
Apr 25 12:39:07 PM PDT 24 |
Apr 25 12:39:23 PM PDT 24 |
30975300 ps |
| T1142 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.161904271 |
|
|
Apr 25 12:39:04 PM PDT 24 |
Apr 25 12:39:19 PM PDT 24 |
36161000 ps |
| T1143 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.94375212 |
|
|
Apr 25 12:38:54 PM PDT 24 |
Apr 25 12:39:12 PM PDT 24 |
20781200 ps |
| T288 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.1005907842 |
|
|
Apr 25 12:39:07 PM PDT 24 |
Apr 25 12:39:23 PM PDT 24 |
37417600 ps |
| T289 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.4271419600 |
|
|
Apr 25 12:38:55 PM PDT 24 |
Apr 25 12:39:58 PM PDT 24 |
3263315700 ps |
| T236 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.3089309075 |
|
|
Apr 25 12:38:42 PM PDT 24 |
Apr 25 12:46:22 PM PDT 24 |
345442700 ps |
| T290 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.436384787 |
|
|
Apr 25 12:38:55 PM PDT 24 |
Apr 25 12:39:14 PM PDT 24 |
71341800 ps |
| T1144 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.1061785131 |
|
|
Apr 25 12:38:44 PM PDT 24 |
Apr 25 12:39:11 PM PDT 24 |
104415200 ps |
| T1145 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.3632085728 |
|
|
Apr 25 12:39:07 PM PDT 24 |
Apr 25 12:39:23 PM PDT 24 |
13468900 ps |
| T1146 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.4031906636 |
|
|
Apr 25 12:39:04 PM PDT 24 |
Apr 25 12:39:21 PM PDT 24 |
21602500 ps |
| T1147 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1622744242 |
|
|
Apr 25 12:38:54 PM PDT 24 |
Apr 25 12:39:14 PM PDT 24 |
95613800 ps |
| T214 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2262321457 |
|
|
Apr 25 12:38:42 PM PDT 24 |
Apr 25 12:39:00 PM PDT 24 |
67599000 ps |
| T1148 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.4029734500 |
|
|
Apr 25 12:38:52 PM PDT 24 |
Apr 25 12:39:07 PM PDT 24 |
15047900 ps |
| T364 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1910175850 |
|
|
Apr 25 12:38:38 PM PDT 24 |
Apr 25 12:38:53 PM PDT 24 |
84055500 ps |
| T218 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.918376366 |
|
|
Apr 25 12:39:14 PM PDT 24 |
Apr 25 12:52:06 PM PDT 24 |
2911958900 ps |
| T215 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.3697529881 |
|
|
Apr 25 12:39:10 PM PDT 24 |
Apr 25 12:39:31 PM PDT 24 |
86940600 ps |
| T216 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.4209576644 |
|
|
Apr 25 12:38:41 PM PDT 24 |
Apr 25 12:38:58 PM PDT 24 |
37706700 ps |
| T1149 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3046310180 |
|
|
Apr 25 12:39:01 PM PDT 24 |
Apr 25 12:39:18 PM PDT 24 |
13982500 ps |
| T1150 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.983375982 |
|
|
Apr 25 12:39:00 PM PDT 24 |
Apr 25 12:39:20 PM PDT 24 |
346951600 ps |
| T325 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.3434061821 |
|
|
Apr 25 12:38:57 PM PDT 24 |
Apr 25 12:39:12 PM PDT 24 |
57565700 ps |
| T409 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.593549951 |
|
|
Apr 25 12:38:59 PM PDT 24 |
Apr 25 12:39:16 PM PDT 24 |
102419700 ps |
| T1151 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.1407778870 |
|
|
Apr 25 12:38:43 PM PDT 24 |
Apr 25 12:38:58 PM PDT 24 |
16463000 ps |
| T353 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.2822507922 |
|
|
Apr 25 12:39:13 PM PDT 24 |
Apr 25 12:39:32 PM PDT 24 |
263913800 ps |
| T1152 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.338049254 |
|
|
Apr 25 12:38:35 PM PDT 24 |
Apr 25 12:38:53 PM PDT 24 |
63779500 ps |
| T219 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1887612943 |
|
|
Apr 25 12:38:55 PM PDT 24 |
Apr 25 12:51:40 PM PDT 24 |
968987200 ps |
| T291 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.872929350 |
|
|
Apr 25 12:39:07 PM PDT 24 |
Apr 25 12:39:26 PM PDT 24 |
43490300 ps |
| T1153 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.3908721782 |
|
|
Apr 25 12:38:56 PM PDT 24 |
Apr 25 12:39:13 PM PDT 24 |
22525100 ps |
| T326 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.565969976 |
|
|
Apr 25 12:38:53 PM PDT 24 |
Apr 25 12:39:09 PM PDT 24 |
24977400 ps |
| T1154 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.311684753 |
|
|
Apr 25 12:38:52 PM PDT 24 |
Apr 25 12:39:10 PM PDT 24 |
43872300 ps |
| T327 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.643537060 |
|
|
Apr 25 12:39:06 PM PDT 24 |
Apr 25 12:39:22 PM PDT 24 |
50472800 ps |
| T217 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.685173164 |
|
|
Apr 25 12:39:00 PM PDT 24 |
Apr 25 12:39:16 PM PDT 24 |
188297800 ps |
| T1155 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.530727058 |
|
|
Apr 25 12:38:44 PM PDT 24 |
Apr 25 12:39:00 PM PDT 24 |
15228400 ps |
| T299 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.3123469163 |
|
|
Apr 25 12:38:49 PM PDT 24 |
Apr 25 12:39:07 PM PDT 24 |
41772200 ps |
| T237 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.148967619 |
|
|
Apr 25 12:38:48 PM PDT 24 |
Apr 25 12:39:06 PM PDT 24 |
37997600 ps |
| T292 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.833172605 |
|
|
Apr 25 12:38:43 PM PDT 24 |
Apr 25 12:39:01 PM PDT 24 |
179482200 ps |
| T1156 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.3695930124 |
|
|
Apr 25 12:39:16 PM PDT 24 |
Apr 25 12:39:36 PM PDT 24 |
15040900 ps |
| T255 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2384707516 |
|
|
Apr 25 12:38:58 PM PDT 24 |
Apr 25 12:39:18 PM PDT 24 |
40016500 ps |
| T355 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.4176226113 |
|
|
Apr 25 12:38:47 PM PDT 24 |
Apr 25 12:45:16 PM PDT 24 |
307430900 ps |
| T1157 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.193774851 |
|
|
Apr 25 12:39:11 PM PDT 24 |
Apr 25 12:39:32 PM PDT 24 |
21528300 ps |
| T250 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2860281414 |
|
|
Apr 25 12:39:04 PM PDT 24 |
Apr 25 12:51:44 PM PDT 24 |
3203989700 ps |
| T1158 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.2959226383 |
|
|
Apr 25 12:39:11 PM PDT 24 |
Apr 25 12:39:30 PM PDT 24 |
29367500 ps |
| T293 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.2774876812 |
|
|
Apr 25 12:39:06 PM PDT 24 |
Apr 25 12:39:23 PM PDT 24 |
259404700 ps |
| T1159 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.1028420964 |
|
|
Apr 25 12:39:09 PM PDT 24 |
Apr 25 12:39:25 PM PDT 24 |
14882500 ps |
| T1160 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.424682751 |
|
|
Apr 25 12:39:02 PM PDT 24 |
Apr 25 12:39:16 PM PDT 24 |
12914500 ps |
| T220 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.272889774 |
|
|
Apr 25 12:39:08 PM PDT 24 |
Apr 25 12:39:24 PM PDT 24 |
245377600 ps |
| T1161 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.203210584 |
|
|
Apr 25 12:38:39 PM PDT 24 |
Apr 25 12:39:27 PM PDT 24 |
6810213500 ps |
| T354 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1225360453 |
|
|
Apr 25 12:38:41 PM PDT 24 |
Apr 25 12:53:54 PM PDT 24 |
9579292600 ps |
| T1162 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.4012520731 |
|
|
Apr 25 12:38:42 PM PDT 24 |
Apr 25 12:38:58 PM PDT 24 |
40125400 ps |
| T1163 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.2661006395 |
|
|
Apr 25 12:38:50 PM PDT 24 |
Apr 25 12:39:09 PM PDT 24 |
28893700 ps |
| T245 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.2220258528 |
|
|
Apr 25 12:38:53 PM PDT 24 |
Apr 25 12:39:13 PM PDT 24 |
120818100 ps |
| T251 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.2597405414 |
|
|
Apr 25 12:39:04 PM PDT 24 |
Apr 25 12:39:22 PM PDT 24 |
66956000 ps |
| T1164 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.386849454 |
|
|
Apr 25 12:39:04 PM PDT 24 |
Apr 25 12:39:22 PM PDT 24 |
29562000 ps |
| T1165 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.3864023456 |
|
|
Apr 25 12:39:03 PM PDT 24 |
Apr 25 12:39:18 PM PDT 24 |
20668600 ps |
| T257 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3798005771 |
|
|
Apr 25 12:38:46 PM PDT 24 |
Apr 25 12:46:22 PM PDT 24 |
3250708700 ps |
| T1166 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.1671606806 |
|
|
Apr 25 12:38:37 PM PDT 24 |
Apr 25 12:38:53 PM PDT 24 |
11270400 ps |
| T1167 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.2707937704 |
|
|
Apr 25 12:38:43 PM PDT 24 |
Apr 25 12:39:03 PM PDT 24 |
130960200 ps |
| T1168 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.3331244526 |
|
|
Apr 25 12:38:37 PM PDT 24 |
Apr 25 12:39:09 PM PDT 24 |
1375530700 ps |
| T221 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1444093491 |
|
|
Apr 25 12:38:36 PM PDT 24 |
Apr 25 12:38:51 PM PDT 24 |
17636700 ps |
| T1169 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.806381579 |
|
|
Apr 25 12:38:54 PM PDT 24 |
Apr 25 12:39:12 PM PDT 24 |
36383100 ps |
| T1170 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2426425237 |
|
|
Apr 25 12:38:44 PM PDT 24 |
Apr 25 12:39:53 PM PDT 24 |
5076999100 ps |
| T1171 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.113282068 |
|
|
Apr 25 12:38:53 PM PDT 24 |
Apr 25 12:39:09 PM PDT 24 |
161040300 ps |
| T258 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.542619831 |
|
|
Apr 25 12:39:00 PM PDT 24 |
Apr 25 12:54:28 PM PDT 24 |
1458975800 ps |
| T294 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.692895922 |
|
|
Apr 25 12:39:07 PM PDT 24 |
Apr 25 12:39:40 PM PDT 24 |
1387336700 ps |
| T253 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.2525659768 |
|
|
Apr 25 12:38:55 PM PDT 24 |
Apr 25 12:39:14 PM PDT 24 |
162452300 ps |
| T1172 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.2477769151 |
|
|
Apr 25 12:38:55 PM PDT 24 |
Apr 25 12:39:13 PM PDT 24 |
28981000 ps |
| T1173 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.3200295354 |
|
|
Apr 25 12:39:14 PM PDT 24 |
Apr 25 12:39:33 PM PDT 24 |
17708200 ps |
| T1174 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.2789466378 |
|
|
Apr 25 12:38:52 PM PDT 24 |
Apr 25 12:39:10 PM PDT 24 |
57331100 ps |
| T1175 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.2832074818 |
|
|
Apr 25 12:39:09 PM PDT 24 |
Apr 25 12:47:01 PM PDT 24 |
345190300 ps |
| T261 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.3584965673 |
|
|
Apr 25 12:38:52 PM PDT 24 |
Apr 25 12:39:11 PM PDT 24 |
45893300 ps |
| T1176 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.2380710873 |
|
|
Apr 25 12:38:37 PM PDT 24 |
Apr 25 12:38:53 PM PDT 24 |
22775300 ps |
| T1177 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.277842527 |
|
|
Apr 25 12:38:58 PM PDT 24 |
Apr 25 12:39:13 PM PDT 24 |
51782700 ps |
| T252 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3685290709 |
|
|
Apr 25 12:39:00 PM PDT 24 |
Apr 25 12:54:06 PM PDT 24 |
1443721100 ps |
| T1178 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.1505780240 |
|
|
Apr 25 12:38:55 PM PDT 24 |
Apr 25 12:39:13 PM PDT 24 |
12638000 ps |
| T1179 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.3798713211 |
|
|
Apr 25 12:39:06 PM PDT 24 |
Apr 25 12:39:22 PM PDT 24 |
47490200 ps |
| T295 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1982330883 |
|
|
Apr 25 12:38:58 PM PDT 24 |
Apr 25 12:39:17 PM PDT 24 |
201596400 ps |
| T244 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.3452821470 |
|
|
Apr 25 12:38:55 PM PDT 24 |
Apr 25 12:39:16 PM PDT 24 |
287590000 ps |
| T1180 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3981017936 |
|
|
Apr 25 12:39:11 PM PDT 24 |
Apr 25 12:39:29 PM PDT 24 |
45100900 ps |
| T1181 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.866086451 |
|
|
Apr 25 12:39:00 PM PDT 24 |
Apr 25 12:39:16 PM PDT 24 |
19570900 ps |
| T1182 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.2203755587 |
|
|
Apr 25 12:38:44 PM PDT 24 |
Apr 25 12:38:59 PM PDT 24 |
29747300 ps |
| T1183 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.763572706 |
|
|
Apr 25 12:38:52 PM PDT 24 |
Apr 25 12:39:07 PM PDT 24 |
14859200 ps |
| T222 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.539133494 |
|
|
Apr 25 12:38:37 PM PDT 24 |
Apr 25 12:38:52 PM PDT 24 |
53010300 ps |
| T1184 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2617940699 |
|
|
Apr 25 12:38:49 PM PDT 24 |
Apr 25 12:39:36 PM PDT 24 |
1106906000 ps |
| T1185 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1199535000 |
|
|
Apr 25 12:38:52 PM PDT 24 |
Apr 25 12:39:28 PM PDT 24 |
161625600 ps |
| T1186 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.2357964112 |
|
|
Apr 25 12:38:42 PM PDT 24 |
Apr 25 12:39:02 PM PDT 24 |
36960900 ps |
| T296 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.3141165215 |
|
|
Apr 25 12:38:57 PM PDT 24 |
Apr 25 12:39:25 PM PDT 24 |
34139200 ps |
| T1187 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.4145261621 |
|
|
Apr 25 12:39:03 PM PDT 24 |
Apr 25 12:39:18 PM PDT 24 |
13613200 ps |
| T256 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1556838674 |
|
|
Apr 25 12:39:03 PM PDT 24 |
Apr 25 12:39:24 PM PDT 24 |
1026513800 ps |
| T1188 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.1850205244 |
|
|
Apr 25 12:39:11 PM PDT 24 |
Apr 25 12:39:30 PM PDT 24 |
55191200 ps |
| T260 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.447402229 |
|
|
Apr 25 12:38:48 PM PDT 24 |
Apr 25 12:39:06 PM PDT 24 |
155103300 ps |
| T1189 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.310757613 |
|
|
Apr 25 12:38:44 PM PDT 24 |
Apr 25 12:38:59 PM PDT 24 |
15033200 ps |
| T254 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.634456321 |
|
|
Apr 25 12:39:10 PM PDT 24 |
Apr 25 12:39:30 PM PDT 24 |
194820100 ps |
| T1190 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.2575122672 |
|
|
Apr 25 12:39:13 PM PDT 24 |
Apr 25 12:39:32 PM PDT 24 |
28194600 ps |
| T1191 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.4219694816 |
|
|
Apr 25 12:39:08 PM PDT 24 |
Apr 25 12:39:24 PM PDT 24 |
38404000 ps |
| T249 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2736373362 |
|
|
Apr 25 12:39:04 PM PDT 24 |
Apr 25 12:39:25 PM PDT 24 |
330728700 ps |
| T1192 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.3091284705 |
|
|
Apr 25 12:39:10 PM PDT 24 |
Apr 25 12:39:30 PM PDT 24 |
30032900 ps |
| T259 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1760626472 |
|
|
Apr 25 12:39:07 PM PDT 24 |
Apr 25 12:39:26 PM PDT 24 |
288557100 ps |
| T223 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.2000819366 |
|
|
Apr 25 12:38:46 PM PDT 24 |
Apr 25 12:39:02 PM PDT 24 |
25479300 ps |
| T1193 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.3068656948 |
|
|
Apr 25 12:38:54 PM PDT 24 |
Apr 25 12:39:30 PM PDT 24 |
377312200 ps |
| T1194 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.3422268673 |
|
|
Apr 25 12:39:08 PM PDT 24 |
Apr 25 12:39:24 PM PDT 24 |
72137200 ps |
| T263 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.237435839 |
|
|
Apr 25 12:38:48 PM PDT 24 |
Apr 25 12:39:06 PM PDT 24 |
192822200 ps |
| T1195 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1643826564 |
|
|
Apr 25 12:39:04 PM PDT 24 |
Apr 25 12:39:20 PM PDT 24 |
47917000 ps |
| T1196 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.2354122830 |
|
|
Apr 25 12:38:49 PM PDT 24 |
Apr 25 12:39:04 PM PDT 24 |
18917400 ps |
| T1197 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.2065709270 |
|
|
Apr 25 12:39:14 PM PDT 24 |
Apr 25 12:39:35 PM PDT 24 |
22891000 ps |
| T1198 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.178716966 |
|
|
Apr 25 12:38:45 PM PDT 24 |
Apr 25 12:39:40 PM PDT 24 |
649156600 ps |
| T1199 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.1624257230 |
|
|
Apr 25 12:39:01 PM PDT 24 |
Apr 25 12:39:16 PM PDT 24 |
61021200 ps |
| T1200 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.280240112 |
|
|
Apr 25 12:38:56 PM PDT 24 |
Apr 25 12:39:12 PM PDT 24 |
91311600 ps |
| T1201 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3461070797 |
|
|
Apr 25 12:38:44 PM PDT 24 |
Apr 25 12:39:03 PM PDT 24 |
170834500 ps |
| T1202 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.1495400004 |
|
|
Apr 25 12:38:39 PM PDT 24 |
Apr 25 12:38:53 PM PDT 24 |
17053200 ps |
| T297 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.2181193083 |
|
|
Apr 25 12:39:04 PM PDT 24 |
Apr 25 12:39:26 PM PDT 24 |
225095900 ps |
| T1203 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3679011630 |
|
|
Apr 25 12:38:54 PM PDT 24 |
Apr 25 12:39:11 PM PDT 24 |
332880100 ps |
| T1204 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3371862058 |
|
|
Apr 25 12:39:03 PM PDT 24 |
Apr 25 12:39:34 PM PDT 24 |
65257900 ps |
| T1205 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.879002548 |
|
|
Apr 25 12:38:48 PM PDT 24 |
Apr 25 12:39:04 PM PDT 24 |
15682600 ps |
| T1206 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.1143590696 |
|
|
Apr 25 12:39:06 PM PDT 24 |
Apr 25 12:39:22 PM PDT 24 |
29532100 ps |
| T1207 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.3601012688 |
|
|
Apr 25 12:38:54 PM PDT 24 |
Apr 25 12:39:11 PM PDT 24 |
25948500 ps |
| T1208 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.2244948368 |
|
|
Apr 25 12:38:46 PM PDT 24 |
Apr 25 12:39:02 PM PDT 24 |
26546200 ps |
| T241 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3030714971 |
|
|
Apr 25 12:38:59 PM PDT 24 |
Apr 25 12:39:17 PM PDT 24 |
40511000 ps |
| T1209 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.2825661059 |
|
|
Apr 25 12:38:51 PM PDT 24 |
Apr 25 12:39:13 PM PDT 24 |
57040700 ps |
| T356 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1194966386 |
|
|
Apr 25 12:39:05 PM PDT 24 |
Apr 25 12:45:36 PM PDT 24 |
464675500 ps |
| T1210 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.2376018606 |
|
|
Apr 25 12:38:51 PM PDT 24 |
Apr 25 12:39:06 PM PDT 24 |
19637100 ps |
| T298 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.71158028 |
|
|
Apr 25 12:39:00 PM PDT 24 |
Apr 25 12:39:37 PM PDT 24 |
202088500 ps |
| T1211 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3766977667 |
|
|
Apr 25 12:39:14 PM PDT 24 |
Apr 25 12:39:35 PM PDT 24 |
677221700 ps |
| T1212 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.1099881160 |
|
|
Apr 25 12:38:46 PM PDT 24 |
Apr 25 12:39:04 PM PDT 24 |
60770400 ps |
| T1213 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1302382285 |
|
|
Apr 25 12:39:11 PM PDT 24 |
Apr 25 12:39:30 PM PDT 24 |
39503800 ps |
| T1214 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.1779538232 |
|
|
Apr 25 12:38:41 PM PDT 24 |
Apr 25 12:38:58 PM PDT 24 |
12547900 ps |
| T1215 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.2900682325 |
|
|
Apr 25 12:38:57 PM PDT 24 |
Apr 25 12:39:12 PM PDT 24 |
25265400 ps |
| T1216 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1400300023 |
|
|
Apr 25 12:39:03 PM PDT 24 |
Apr 25 12:39:20 PM PDT 24 |
26536700 ps |
| T1217 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.1947716517 |
|
|
Apr 25 12:39:07 PM PDT 24 |
Apr 25 12:39:23 PM PDT 24 |
52793300 ps |
| T1218 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.552883472 |
|
|
Apr 25 12:38:59 PM PDT 24 |
Apr 25 12:39:13 PM PDT 24 |
17957600 ps |
| T362 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.583400246 |
|
|
Apr 25 12:38:46 PM PDT 24 |
Apr 25 12:46:32 PM PDT 24 |
1378887000 ps |
| T1219 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.1174159709 |
|
|
Apr 25 12:38:57 PM PDT 24 |
Apr 25 12:39:15 PM PDT 24 |
59857600 ps |
| T1220 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3034207359 |
|
|
Apr 25 12:39:03 PM PDT 24 |
Apr 25 12:39:18 PM PDT 24 |
19118700 ps |
| T1221 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.2427085041 |
|
|
Apr 25 12:38:56 PM PDT 24 |
Apr 25 12:39:12 PM PDT 24 |
80851800 ps |
| T1222 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.3210555601 |
|
|
Apr 25 12:39:03 PM PDT 24 |
Apr 25 12:39:19 PM PDT 24 |
19119600 ps |
| T262 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.2397508742 |
|
|
Apr 25 12:39:00 PM PDT 24 |
Apr 25 12:39:19 PM PDT 24 |
37705600 ps |
| T1223 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3739897123 |
|
|
Apr 25 12:38:54 PM PDT 24 |
Apr 25 12:39:13 PM PDT 24 |
260824300 ps |
| T357 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.3144743230 |
|
|
Apr 25 12:39:00 PM PDT 24 |
Apr 25 12:51:45 PM PDT 24 |
371268700 ps |
| T242 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2476712450 |
|
|
Apr 25 12:39:11 PM PDT 24 |
Apr 25 12:39:31 PM PDT 24 |
47824000 ps |
| T1224 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.117228198 |
|
|
Apr 25 12:39:06 PM PDT 24 |
Apr 25 12:39:26 PM PDT 24 |
212398000 ps |
| T1225 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.1889684214 |
|
|
Apr 25 12:39:03 PM PDT 24 |
Apr 25 12:39:18 PM PDT 24 |
32591700 ps |
| T1226 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.2284327099 |
|
|
Apr 25 12:39:03 PM PDT 24 |
Apr 25 12:39:17 PM PDT 24 |
24681000 ps |
| T1227 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.3018266065 |
|
|
Apr 25 12:38:45 PM PDT 24 |
Apr 25 12:39:03 PM PDT 24 |
19209900 ps |
| T1228 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.2321416569 |
|
|
Apr 25 12:39:16 PM PDT 24 |
Apr 25 12:39:36 PM PDT 24 |
31755900 ps |
| T1229 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.176365053 |
|
|
Apr 25 12:39:13 PM PDT 24 |
Apr 25 12:39:31 PM PDT 24 |
160646300 ps |
| T359 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.1147356106 |
|
|
Apr 25 12:39:02 PM PDT 24 |
Apr 25 12:54:26 PM PDT 24 |
9459714800 ps |
| T1230 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.1173656082 |
|
|
Apr 25 12:39:01 PM PDT 24 |
Apr 25 12:39:18 PM PDT 24 |
24896500 ps |
| T1231 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.2881837092 |
|
|
Apr 25 12:38:54 PM PDT 24 |
Apr 25 12:39:12 PM PDT 24 |
151295700 ps |
| T1232 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.3023861698 |
|
|
Apr 25 12:38:54 PM PDT 24 |
Apr 25 12:39:11 PM PDT 24 |
162598500 ps |
| T1233 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.341541195 |
|
|
Apr 25 12:38:41 PM PDT 24 |
Apr 25 12:38:56 PM PDT 24 |
15802700 ps |
| T1234 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2337484808 |
|
|
Apr 25 12:38:52 PM PDT 24 |
Apr 25 12:39:07 PM PDT 24 |
18605100 ps |
| T1235 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1112183422 |
|
|
Apr 25 12:38:44 PM PDT 24 |
Apr 25 12:39:02 PM PDT 24 |
17478800 ps |
| T1236 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2056488621 |
|
|
Apr 25 12:39:01 PM PDT 24 |
Apr 25 12:39:18 PM PDT 24 |
14482400 ps |
| T1237 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.2811623929 |
|
|
Apr 25 12:39:10 PM PDT 24 |
Apr 25 12:39:27 PM PDT 24 |
51320500 ps |
| T1238 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.1515678046 |
|
|
Apr 25 12:38:47 PM PDT 24 |
Apr 25 12:39:03 PM PDT 24 |
45262300 ps |
| T243 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.4187155904 |
|
|
Apr 25 12:39:03 PM PDT 24 |
Apr 25 12:39:21 PM PDT 24 |
46633100 ps |
| T1239 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.2522489926 |
|
|
Apr 25 12:38:50 PM PDT 24 |
Apr 25 12:39:07 PM PDT 24 |
183948500 ps |
| T1240 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.2291254813 |
|
|
Apr 25 12:38:59 PM PDT 24 |
Apr 25 12:39:15 PM PDT 24 |
17773100 ps |
| T1241 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.1428847838 |
|
|
Apr 25 12:39:13 PM PDT 24 |
Apr 25 12:39:36 PM PDT 24 |
76016200 ps |
| T1242 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.827208331 |
|
|
Apr 25 12:39:05 PM PDT 24 |
Apr 25 12:39:21 PM PDT 24 |
24558800 ps |
| T1243 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.952787197 |
|
|
Apr 25 12:39:00 PM PDT 24 |
Apr 25 12:39:18 PM PDT 24 |
24564000 ps |
| T1244 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.3597700343 |
|
|
Apr 25 12:38:45 PM PDT 24 |
Apr 25 12:39:47 PM PDT 24 |
659843500 ps |
| T1245 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.2617211670 |
|
|
Apr 25 12:39:01 PM PDT 24 |
Apr 25 12:39:18 PM PDT 24 |
62988300 ps |
| T360 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.1259130541 |
|
|
Apr 25 12:38:36 PM PDT 24 |
Apr 25 12:46:16 PM PDT 24 |
685797100 ps |
| T1246 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.426398044 |
|
|
Apr 25 12:39:04 PM PDT 24 |
Apr 25 12:39:20 PM PDT 24 |
145060400 ps |
| T1247 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.1442739204 |
|
|
Apr 25 12:38:54 PM PDT 24 |
Apr 25 12:39:09 PM PDT 24 |
47187400 ps |
| T1248 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3154767606 |
|
|
Apr 25 12:38:55 PM PDT 24 |
Apr 25 12:39:10 PM PDT 24 |
53409900 ps |
| T1249 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.3472014332 |
|
|
Apr 25 12:38:54 PM PDT 24 |
Apr 25 12:39:58 PM PDT 24 |
4939484600 ps |
| T1250 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.1734422318 |
|
|
Apr 25 12:38:48 PM PDT 24 |
Apr 25 12:39:05 PM PDT 24 |
34112600 ps |
| T1251 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.1752211192 |
|
|
Apr 25 12:38:59 PM PDT 24 |
Apr 25 12:39:19 PM PDT 24 |
476640100 ps |
| T1252 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.3031931475 |
|
|
Apr 25 12:38:58 PM PDT 24 |
Apr 25 12:39:17 PM PDT 24 |
329283000 ps |
| T1253 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.4150985355 |
|
|
Apr 25 12:38:40 PM PDT 24 |
Apr 25 12:39:39 PM PDT 24 |
647535000 ps |