Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	328450	1		T1	1		T2	25		T3	2
all_values[1]	328450	1		T1	1		T2	25		T3	2
all_values[2]	328450	1		T1	1		T2	25		T3	2
all_values[3]	328450	1		T1	1		T2	25		T3	2
all_values[4]	328450	1		T1	1		T2	25		T3	2
all_values[5]	328450	1		T1	1		T2	25		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	662309	1		T1	6		T2	150		T3	12
auto[1]	1308391	1		T12	5352		T13	6728		T14	7128

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	961144	1		T1	4		T2	90		T3	7
auto[1]	1009556	1		T1	2		T2	60		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	328287	1		T1	1		T2	25		T3	2
all_values[0]	auto[1]	auto[1]	163	1		T268	3		T269	2		T270	5
all_values[1]	auto[0]	auto[1]	328274	1		T1	1		T2	25		T3	2
all_values[1]	auto[1]	auto[1]	176	1		T268	1		T269	4		T270	3
all_values[2]	auto[0]	auto[0]	1383	1		T1	1		T2	25		T3	2
all_values[2]	auto[0]	auto[1]	62	1		T268	1		T269	2		T270	1
all_values[2]	auto[1]	auto[0]	326945	1		T12	1338		T13	1682		T14	1782
all_values[2]	auto[1]	auto[1]	60	1		T268	2		T270	2		T325	1
all_values[3]	auto[0]	auto[0]	1385	1		T1	1		T2	25		T3	2
all_values[3]	auto[0]	auto[1]	46	1		T268	2		T269	2		T326	3
all_values[3]	auto[1]	auto[0]	52171	1		T12	669		T13	841		T14	891
all_values[3]	auto[1]	auto[1]	274848	1		T12	669		T13	841		T14	891
all_values[4]	auto[0]	auto[0]	978	1		T1	1		T2	15		T3	1
all_values[4]	auto[0]	auto[1]	456	1		T2	10		T3	1		T5	1
all_values[4]	auto[1]	auto[0]	249991	1		T12	669		T13	841		T14	891
all_values[4]	auto[1]	auto[1]	77025	1		T12	669		T13	841		T14	891
all_values[5]	auto[0]	auto[0]	1337	1		T1	1		T2	25		T3	2
all_values[5]	auto[0]	auto[1]	101	1		T42	1		T80	1		T11	1
all_values[5]	auto[1]	auto[0]	326954	1		T12	1338		T13	1682		T14	1782
all_values[5]	auto[1]	auto[1]	58	1		T268	2		T270	1		T326	2