Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
206 |
1 |
|
T2 |
2 |
|
T128 |
6 |
|
T30 |
1 |
| others[1] |
204 |
1 |
|
T2 |
2 |
|
T5 |
1 |
|
T15 |
1 |
| others[2] |
218 |
1 |
|
T2 |
1 |
|
T128 |
9 |
|
T11 |
1 |
| others[3] |
384 |
1 |
|
T2 |
1 |
|
T128 |
15 |
|
T198 |
2 |
| false |
127 |
1 |
|
T2 |
1 |
|
T128 |
4 |
|
T118 |
6 |
| true |
12621 |
1 |
|
T1 |
1 |
|
T2 |
10 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8245 |
1 |
|
T2 |
3 |
|
T4 |
66 |
|
T9 |
2 |
| others[1] |
1230 |
1 |
|
T2 |
3 |
|
T5 |
1 |
|
T10 |
1 |
| others[2] |
1149 |
1 |
|
T2 |
2 |
|
T10 |
1 |
|
T16 |
11 |
| others[3] |
2129 |
1 |
|
T2 |
8 |
|
T10 |
4 |
|
T16 |
18 |
| false |
661 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T16 |
3 |
| true |
346 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8264 |
1 |
|
T2 |
4 |
|
T4 |
66 |
|
T9 |
2 |
| others[1] |
1226 |
1 |
|
T2 |
4 |
|
T10 |
1 |
|
T16 |
6 |
| others[2] |
1214 |
1 |
|
T2 |
2 |
|
T5 |
1 |
|
T10 |
2 |
| others[3] |
2122 |
1 |
|
T1 |
1 |
|
T2 |
5 |
|
T10 |
1 |
| false |
626 |
1 |
|
T2 |
2 |
|
T10 |
2 |
|
T16 |
5 |
| true |
308 |
1 |
|
T3 |
1 |
|
T24 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
113 |
1 |
|
T2 |
6 |
|
T128 |
3 |
|
T196 |
1 |
| others[1] |
115 |
1 |
|
T2 |
2 |
|
T128 |
3 |
|
T118 |
2 |
| others[2] |
101 |
1 |
|
T2 |
2 |
|
T128 |
2 |
|
T118 |
2 |
| others[3] |
171 |
1 |
|
T2 |
4 |
|
T5 |
1 |
|
T128 |
5 |
| false |
46 |
1 |
|
T2 |
3 |
|
T128 |
3 |
|
T196 |
1 |
| true |
13214 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
66 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T2 |
1 |
|
T128 |
12 |
|
T118 |
6 |
| others[1] |
249 |
1 |
|
T2 |
3 |
|
T5 |
1 |
|
T77 |
3 |
| others[2] |
216 |
1 |
|
T77 |
2 |
|
T42 |
1 |
|
T128 |
8 |
| others[3] |
359 |
1 |
|
T2 |
2 |
|
T128 |
16 |
|
T196 |
1 |
| false |
117 |
1 |
|
T2 |
1 |
|
T77 |
1 |
|
T128 |
6 |
| true |
12599 |
1 |
|
T1 |
1 |
|
T2 |
10 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8049 |
1 |
|
T1 |
1 |
|
T2 |
7 |
|
T4 |
66 |
| others[1] |
987 |
1 |
|
T2 |
1 |
|
T10 |
3 |
|
T15 |
1 |
| others[2] |
1074 |
1 |
|
T2 |
2 |
|
T10 |
1 |
|
T16 |
8 |
| others[3] |
1767 |
1 |
|
T2 |
6 |
|
T3 |
1 |
|
T5 |
1 |
| false |
554 |
1 |
|
T2 |
1 |
|
T24 |
1 |
|
T10 |
2 |
| true |
1329 |
1 |
|
T61 |
1 |
|
T42 |
1 |
|
T45 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T2 |
1 |
|
T77 |
2 |
|
T128 |
13 |
| others[1] |
219 |
1 |
|
T2 |
2 |
|
T128 |
10 |
|
T196 |
1 |
| others[2] |
214 |
1 |
|
T2 |
4 |
|
T15 |
1 |
|
T77 |
1 |
| others[3] |
387 |
1 |
|
T2 |
2 |
|
T3 |
1 |
|
T77 |
1 |
| false |
113 |
1 |
|
T77 |
2 |
|
T128 |
4 |
|
T118 |
1 |
| true |
12600 |
1 |
|
T1 |
1 |
|
T2 |
8 |
|
T4 |
66 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T2 |
2 |
|
T15 |
1 |
|
T128 |
11 |
| others[1] |
251 |
1 |
|
T2 |
1 |
|
T128 |
8 |
|
T118 |
16 |
| others[2] |
217 |
1 |
|
T5 |
1 |
|
T128 |
11 |
|
T197 |
1 |
| others[3] |
357 |
1 |
|
T2 |
2 |
|
T42 |
1 |
|
T128 |
10 |
| false |
92 |
1 |
|
T2 |
1 |
|
T128 |
6 |
|
T118 |
5 |
| true |
12616 |
1 |
|
T1 |
1 |
|
T2 |
11 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8252 |
1 |
|
T4 |
66 |
|
T9 |
2 |
|
T21 |
2 |
| others[1] |
1208 |
1 |
|
T2 |
3 |
|
T10 |
1 |
|
T16 |
9 |
| others[2] |
1278 |
1 |
|
T2 |
6 |
|
T16 |
9 |
|
T50 |
12 |
| others[3] |
2071 |
1 |
|
T2 |
7 |
|
T5 |
1 |
|
T10 |
5 |
| false |
626 |
1 |
|
T2 |
1 |
|
T10 |
2 |
|
T16 |
6 |
| true |
325 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1220 |
1 |
|
T2 |
2 |
|
T10 |
1 |
|
T16 |
8 |
| others[1] |
1251 |
1 |
|
T2 |
4 |
|
T5 |
1 |
|
T10 |
1 |
| others[2] |
1183 |
1 |
|
T2 |
4 |
|
T10 |
1 |
|
T16 |
6 |
| others[3] |
2133 |
1 |
|
T2 |
6 |
|
T10 |
4 |
|
T16 |
19 |
| false |
643 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T16 |
6 |
| true |
307 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
94 |
1 |
|
T2 |
5 |
|
T128 |
3 |
|
T118 |
4 |
| others[1] |
97 |
1 |
|
T2 |
3 |
|
T128 |
7 |
|
T118 |
6 |
| others[2] |
119 |
1 |
|
T2 |
2 |
|
T3 |
1 |
|
T128 |
6 |
| others[3] |
169 |
1 |
|
T2 |
4 |
|
T5 |
1 |
|
T128 |
2 |
| false |
59 |
1 |
|
T2 |
3 |
|
T128 |
3 |
|
T198 |
1 |
| true |
6199 |
1 |
|
T1 |
1 |
|
T24 |
1 |
|
T10 |
8 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
238 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T128 |
10 |
| others[1] |
213 |
1 |
|
T2 |
3 |
|
T3 |
1 |
|
T15 |
1 |
| others[2] |
207 |
1 |
|
T128 |
8 |
|
T197 |
1 |
|
T118 |
8 |
| others[3] |
374 |
1 |
|
T2 |
3 |
|
T128 |
20 |
|
T196 |
1 |
| false |
131 |
1 |
|
T2 |
1 |
|
T42 |
1 |
|
T128 |
5 |
| true |
5574 |
1 |
|
T1 |
1 |
|
T2 |
9 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1113 |
1 |
|
T2 |
1 |
|
T10 |
2 |
|
T16 |
10 |
| others[1] |
1056 |
1 |
|
T2 |
3 |
|
T10 |
2 |
|
T16 |
8 |
| others[2] |
1015 |
1 |
|
T2 |
4 |
|
T10 |
4 |
|
T16 |
12 |
| others[3] |
1709 |
1 |
|
T2 |
4 |
|
T3 |
1 |
|
T5 |
1 |
| false |
577 |
1 |
|
T2 |
5 |
|
T16 |
5 |
|
T42 |
1 |
| true |
1267 |
1 |
|
T1 |
1 |
|
T24 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T2 |
3 |
|
T128 |
14 |
|
T118 |
6 |
| others[1] |
230 |
1 |
|
T2 |
2 |
|
T128 |
11 |
|
T80 |
1 |
| others[2] |
208 |
1 |
|
T2 |
2 |
|
T128 |
8 |
|
T118 |
7 |
| others[3] |
370 |
1 |
|
T2 |
4 |
|
T128 |
16 |
|
T30 |
1 |
| false |
129 |
1 |
|
T42 |
1 |
|
T128 |
6 |
|
T196 |
1 |
| true |
5582 |
1 |
|
T1 |
1 |
|
T2 |
6 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T2 |
2 |
|
T128 |
12 |
|
T118 |
13 |
| others[1] |
212 |
1 |
|
T2 |
2 |
|
T42 |
1 |
|
T128 |
14 |
| others[2] |
213 |
1 |
|
T2 |
1 |
|
T128 |
2 |
|
T196 |
1 |
| others[3] |
380 |
1 |
|
T2 |
2 |
|
T3 |
1 |
|
T5 |
1 |
| false |
119 |
1 |
|
T2 |
1 |
|
T128 |
12 |
|
T196 |
1 |
| true |
5586 |
1 |
|
T1 |
1 |
|
T2 |
9 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1211 |
1 |
|
T2 |
4 |
|
T10 |
2 |
|
T16 |
9 |
| others[1] |
1206 |
1 |
|
T2 |
5 |
|
T5 |
1 |
|
T16 |
4 |
| others[2] |
1332 |
1 |
|
T2 |
6 |
|
T10 |
2 |
|
T16 |
11 |
| others[3] |
2025 |
1 |
|
T2 |
2 |
|
T10 |
3 |
|
T15 |
1 |
| false |
622 |
1 |
|
T10 |
1 |
|
T16 |
5 |
|
T33 |
1 |
| true |
341 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1220 |
1 |
|
T2 |
4 |
|
T10 |
1 |
|
T16 |
11 |
| others[1] |
1224 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T16 |
9 |
| others[2] |
1195 |
1 |
|
T2 |
7 |
|
T10 |
2 |
|
T16 |
5 |
| others[3] |
2089 |
1 |
|
T2 |
4 |
|
T5 |
1 |
|
T10 |
4 |
| false |
700 |
1 |
|
T2 |
1 |
|
T16 |
10 |
|
T50 |
3 |
| true |
309 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
110 |
1 |
|
T2 |
3 |
|
T3 |
1 |
|
T128 |
5 |
| others[1] |
100 |
1 |
|
T2 |
6 |
|
T128 |
3 |
|
T118 |
9 |
| others[2] |
96 |
1 |
|
T2 |
1 |
|
T128 |
4 |
|
T196 |
1 |
| others[3] |
181 |
1 |
|
T2 |
3 |
|
T42 |
1 |
|
T128 |
11 |
| false |
62 |
1 |
|
T2 |
4 |
|
T197 |
1 |
|
T118 |
4 |
| true |
6188 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T2 |
4 |
|
T5 |
1 |
|
T128 |
9 |
| others[1] |
238 |
1 |
|
T2 |
1 |
|
T61 |
1 |
|
T128 |
14 |
| others[2] |
235 |
1 |
|
T2 |
1 |
|
T128 |
10 |
|
T80 |
1 |
| others[3] |
384 |
1 |
|
T2 |
4 |
|
T128 |
20 |
|
T196 |
2 |
| false |
121 |
1 |
|
T128 |
5 |
|
T118 |
9 |
|
T136 |
5 |
| true |
5526 |
1 |
|
T1 |
1 |
|
T2 |
7 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
997 |
1 |
|
T1 |
1 |
|
T2 |
5 |
|
T10 |
2 |
| others[1] |
1038 |
1 |
|
T2 |
2 |
|
T16 |
8 |
|
T77 |
1 |
| others[2] |
1050 |
1 |
|
T2 |
2 |
|
T10 |
4 |
|
T15 |
1 |
| others[3] |
1731 |
1 |
|
T2 |
7 |
|
T5 |
1 |
|
T10 |
1 |
| false |
562 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T16 |
3 |
| true |
1359 |
1 |
|
T3 |
1 |
|
T24 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
213 |
1 |
|
T2 |
4 |
|
T128 |
6 |
|
T118 |
6 |
| others[1] |
226 |
1 |
|
T2 |
2 |
|
T128 |
9 |
|
T196 |
1 |
| others[2] |
236 |
1 |
|
T128 |
11 |
|
T118 |
13 |
|
T136 |
15 |
| others[3] |
369 |
1 |
|
T2 |
4 |
|
T128 |
20 |
|
T134 |
1 |
| false |
133 |
1 |
|
T2 |
2 |
|
T128 |
4 |
|
T118 |
7 |
| true |
5560 |
1 |
|
T1 |
1 |
|
T2 |
5 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
238 |
1 |
|
T2 |
2 |
|
T15 |
1 |
|
T128 |
6 |
| others[1] |
205 |
1 |
|
T2 |
1 |
|
T128 |
4 |
|
T118 |
8 |
| others[2] |
228 |
1 |
|
T128 |
9 |
|
T197 |
1 |
|
T11 |
1 |
| others[3] |
361 |
1 |
|
T2 |
2 |
|
T128 |
14 |
|
T196 |
1 |
| false |
114 |
1 |
|
T2 |
3 |
|
T128 |
8 |
|
T30 |
1 |
| true |
5591 |
1 |
|
T1 |
1 |
|
T2 |
9 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1268 |
1 |
|
T2 |
6 |
|
T10 |
4 |
|
T16 |
15 |
| others[1] |
1193 |
1 |
|
T5 |
1 |
|
T10 |
1 |
|
T16 |
7 |
| others[2] |
1212 |
1 |
|
T2 |
2 |
|
T10 |
1 |
|
T16 |
5 |
| others[3] |
2083 |
1 |
|
T2 |
9 |
|
T10 |
1 |
|
T16 |
14 |
| false |
639 |
1 |
|
T10 |
1 |
|
T16 |
4 |
|
T50 |
3 |
| true |
342 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1213 |
1 |
|
T2 |
3 |
|
T10 |
2 |
|
T16 |
6 |
| others[1] |
1267 |
1 |
|
T2 |
2 |
|
T10 |
2 |
|
T16 |
7 |
| others[2] |
1186 |
1 |
|
T2 |
5 |
|
T10 |
2 |
|
T16 |
7 |
| others[3] |
2137 |
1 |
|
T2 |
5 |
|
T5 |
1 |
|
T10 |
2 |
| false |
625 |
1 |
|
T2 |
2 |
|
T16 |
2 |
|
T36 |
4 |
| true |
309 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
114 |
1 |
|
T2 |
2 |
|
T128 |
3 |
|
T196 |
2 |
| others[1] |
104 |
1 |
|
T2 |
6 |
|
T128 |
1 |
|
T196 |
1 |
| others[2] |
118 |
1 |
|
T2 |
4 |
|
T5 |
1 |
|
T128 |
7 |
| others[3] |
184 |
1 |
|
T2 |
4 |
|
T128 |
5 |
|
T118 |
7 |
| false |
61 |
1 |
|
T2 |
1 |
|
T128 |
1 |
|
T198 |
1 |
| true |
6156 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T128 |
11 |
| others[1] |
237 |
1 |
|
T2 |
6 |
|
T77 |
1 |
|
T128 |
4 |
| others[2] |
243 |
1 |
|
T2 |
1 |
|
T77 |
3 |
|
T128 |
13 |
| others[3] |
348 |
1 |
|
T3 |
1 |
|
T61 |
1 |
|
T77 |
2 |
| false |
116 |
1 |
|
T2 |
1 |
|
T128 |
3 |
|
T229 |
1 |
| true |
5569 |
1 |
|
T1 |
1 |
|
T2 |
8 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1027 |
1 |
|
T2 |
5 |
|
T5 |
1 |
|
T24 |
1 |
| others[1] |
1013 |
1 |
|
T2 |
3 |
|
T10 |
1 |
|
T16 |
8 |
| others[2] |
1086 |
1 |
|
T2 |
4 |
|
T10 |
1 |
|
T16 |
9 |
| others[3] |
1749 |
1 |
|
T2 |
2 |
|
T10 |
4 |
|
T20 |
1 |
| false |
567 |
1 |
|
T2 |
3 |
|
T16 |
5 |
|
T36 |
1 |
| true |
1295 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
223 |
1 |
|
T2 |
1 |
|
T128 |
6 |
|
T48 |
1 |
| others[1] |
191 |
1 |
|
T2 |
4 |
|
T5 |
1 |
|
T128 |
8 |
| others[2] |
237 |
1 |
|
T128 |
9 |
|
T229 |
1 |
|
T118 |
8 |
| others[3] |
386 |
1 |
|
T2 |
4 |
|
T42 |
1 |
|
T128 |
18 |
| false |
116 |
1 |
|
T3 |
1 |
|
T128 |
10 |
|
T118 |
6 |
| true |
5584 |
1 |
|
T1 |
1 |
|
T2 |
8 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T2 |
2 |
|
T15 |
1 |
|
T128 |
9 |
| others[1] |
234 |
1 |
|
T2 |
4 |
|
T3 |
1 |
|
T128 |
16 |
| others[2] |
185 |
1 |
|
T2 |
2 |
|
T128 |
7 |
|
T118 |
9 |
| others[3] |
402 |
1 |
|
T2 |
1 |
|
T128 |
20 |
|
T48 |
1 |
| false |
100 |
1 |
|
T128 |
1 |
|
T118 |
4 |
|
T136 |
4 |
| true |
5587 |
1 |
|
T1 |
1 |
|
T2 |
8 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1234 |
1 |
|
T2 |
4 |
|
T5 |
1 |
|
T10 |
3 |
| others[1] |
1246 |
1 |
|
T2 |
5 |
|
T10 |
1 |
|
T16 |
9 |
| others[2] |
1224 |
1 |
|
T2 |
3 |
|
T10 |
1 |
|
T16 |
6 |
| others[3] |
2052 |
1 |
|
T2 |
3 |
|
T10 |
3 |
|
T16 |
8 |
| false |
650 |
1 |
|
T2 |
2 |
|
T16 |
6 |
|
T36 |
3 |
| true |
331 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1339 |
1 |
|
T1 |
1 |
|
T2 |
4 |
|
T5 |
1 |
| others[1] |
1201 |
1 |
|
T2 |
3 |
|
T10 |
1 |
|
T16 |
6 |
| others[2] |
1201 |
1 |
|
T2 |
2 |
|
T10 |
4 |
|
T16 |
11 |
| others[3] |
2050 |
1 |
|
T2 |
7 |
|
T10 |
2 |
|
T16 |
15 |
| false |
642 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T16 |
5 |
| true |
304 |
1 |
|
T3 |
1 |
|
T24 |
1 |
|
T20 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |